Intel BX80623I52500K Specification Update
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- Intel BX80623I52500K | Specification Update - Page 1
Intel® Pentium® 4 Processor Specification Update August 2008 Revision 071 Document Number: 249199-071 - Intel BX80623I52500K | Specification Update - Page 2
or your distributor to obtain the latest specifications and before placing your product order. Intel, Intel Pentium 4 processor, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands - Intel BX80623I52500K | Specification Update - Page 3
Contents Preface...9 Summary Tables of Changes 11 General Information ...21 Identification Information 24 Errata ...31 Specification Changes...69 Specification Clarifications 70 Documentation Changes 74 § Specification Update 3 - Intel BX80623I52500K | Specification Update - Page 4
N19, N21, N23 - N28, N30 - N35, and N41 • Added information for the Intel® Pentium® 4 processor in the 478-pin package, Added erratum N48. • ® ® Updated the Intel Pentium 4 Processor Identification Information table. Added erratum N49. • Updated Specification Update product key to include the - Intel BX80623I52500K | Specification Update - Page 5
Changes N3 and N4. Added Documentation Changes N33-42. • Added eight S-spec numbers under identification information table. • Added Errata N69 and N70. • Added Erratum N71. • Added full graphics range to General Information section. Minor typographical errors from text conversion corrected - Intel BX80623I52500K | Specification Update - Page 6
Erratum N85 and Updated Erratum N83. • Release 3.40 GHz Intel® Pentium® 4 Processor Extreme Edition Supporting Hyper-Threading Technology. • Added S-Spec number under identification information table. • Added Intel® Pentium® 4 processor on 90 nm process. • Removed Specification Change N2. • Removed - Intel BX80623I52500K | Specification Update - Page 7
its link o Added S-spec number SL7GD • Added S-Spec number under identification information • Updated processor identification table, and added Errata N96- 97 • Added 1066 Products in processor identification table • Updated links to Software Developers Manuals. March 2006 -064 • Added errata - Intel BX80623I52500K | Specification Update - Page 8
Revision -069 -070 -071 Description • Updated Summary Table of Changes. • Updated Summary Table of Changes. • Updated Summary Table of Changes § Date May 2007 April 2008 August 2008 8 Specification Update - Intel BX80623I52500K | Specification Update - Page 9
-pin Package datasheet Intel® Pentium® 4 Processor in the 478-pin Package datasheet Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process and Intel® Pentium® 4 Processor Extreme Edition Supporting Hyper-Threading Technology1 datasheet Intel® Pentium® 4 Processor Extreme Edition on - Intel BX80623I52500K | Specification Update - Page 10
32 Intel Architectures Software Developer's Manual Volume 3A: System Programming Guide Intel® 64 and IA-32 Intel Architectures Software Developer's Manual Volume 3B: System Programming Guide Nomenclature Errata are design defects or errors. Errata may cause the Intel® Pentium® 4 processor's behavior - Intel BX80623I52500K | Specification Update - Page 11
with a capital letter to distinguish the product. The key below details the letters that are used in Intel's microprocessor Specification Updates: A = Dual-Core Intel® Xeon® processor 7000 sequence C = Intel® Celeron® processor D = Dual-Core Intel® Xeon® processor 2.80 GHz Specification Update 11 - Intel BX80623I52500K | Specification Update - Page 12
Intel® Pentium® 4 processor 6x1 sequence Intel(R) Celeron(R) processor in 478 pin package Intel(R) Celeron(R) D processor on 65nm process Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65nm process Dual-Core Intel® Xeon® processor LV Dual-Core Intel® Xeon® processor 5100 series Intel - Intel BX80623I52500K | Specification Update - Page 13
Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45- nm Process AAA = Quad-Core Intel® Xeon® processor 3300 series AAB = Dual-Core Intel® Xeon® E3110 Processor AAC = Intel® Celeron® dual-core processor E1000 series AAD = Intel® Core™2 Extreme Processor QX9775Δ AAE = Intel® Atom™ processor - Intel BX80623I52500K | Specification Update - Page 14
of uncacheable (UC) FSW may not be completely restored N8 X X X X X X X X No Fix after page fault on FRSTOR or FLDENV instructions The Processor Signals Page-Fault Exception N9 X X X X X X X X No Fix (#PF) Instead of Alignment Check Exception (#AC) on an Unlocked CMPXCHG8B - Intel BX80623I52500K | Specification Update - Page 15
for an L1 tag parity error is logged in IA32_MC1_ADDR register N29 X X Fixed REP MOV instruction with overlapping source and destination may result in data corruption N30 X Fixed Stale data in processor translation cache may result in hang N31 X Fixed I/O buffers for FERR#, PROCHOT# and - Intel BX80623I52500K | Specification Update - Page 16
may not work as expected N44 X X X X Fixed Software controlled clock modulation using a 12.5% or 25% duty cycle may cause the processor to hang N45 X X Fixed Speculative page fault may cause livelock N46 X X Fixed PAT index MSB may be calculated incorrectly N47 X X X Fixed - Intel BX80623I52500K | Specification Update - Page 17
be incorrect or an incorrect page fault error code may be pushed onto stack after execution of an LSS instruction N59 X Fixed BPM[5:3]# VIL does not meet specification N60 Processor may hang under certain X X X X No Fix frequencies and 12.5% STPCLK# duty cycle System may hang if a fatal - Intel BX80623I52500K | Specification Update - Page 18
X X X X X No Fix Changes to CR3 Register do not Fence Pending Instruction Page Walks The State of the Resume Flag (RF Flag) N77 X X X May be Incorrect N78 X X X X X X X X No Fix Processor Provides a 4-Byte Store Unlock After an 8-Byte Load Lock N79 Simultaneous Page Faults - Intel BX80623I52500K | Specification Update - Page 19
of Instruction BTS(Branch Trace Store) and PEBS(Precise N97 X X X X X X X X No Fix Event Based Sampling) May Update Memory outside the BTS/PEBS Buffer N98 Brand String Field Reports Incorrect Maximum X No Fix Operating Frequency on Intel® Pentium® 4 Extreme Edition Processor with - Intel BX80623I52500K | Specification Update - Page 20
Summary Tables of Changes No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA when an Interrupt is Pending May Cause an Unexpected Interrupt Using 2M/4M Pages When A20M# Is N102 X X X X X X X X No Fix Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that N103 X - Intel BX80623I52500K | Specification Update - Page 21
/400/1.7V SLY4YSYHY MXXAXLAXYXX F1F2F384F5F6F7FF-1-N27N2NN i m c '00 Frequency/Cache/Bus/Voltage 2-D Matrix Mark Figure 2 Intel® Pentium® 4 Processor in the 478-Pin Package Markings Example 1 S-Spec/Country of Assy FPO - Serial # 2 GHZ/256/400/1.75V SYYYY XXXXXX FFFFFFFF-NNNN i ©'01 Frequency - Intel BX80623I52500K | Specification Update - Page 22
-KB L2 Cache on 0.13 Micron Process, Intel® Pentium® 4 Processor Extreme Edition Supporting Hyper-Threading Technology, and Boxed Pentium 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Processor Markings S-Spec/Country of Assy FPO - Serial # INTEL m c `01 PENTIUM® 4 2.40 GHZ/512/800/1.50V - Intel BX80623I52500K | Specification Update - Page 23
General Information Figure 7 Intel® Pentium® 4 Extreme Edition on 0.13 micron in the 775-Land LGA Package Marking S-Spec/ Country of Assy FPO 2-D Matrix Mark INTEL m c `04 PENTIUM® 4 3.40 GHZ/512/800 SYYYY XXXXXX FFFFFFFF ATTPO S/N Frequency/ L2 Cache/ Bus Unique Unit Identifier ATPO Serial # - Intel BX80623I52500K | Specification Update - Page 24
the CPUID instruction is executed with a 1 in the EAX register. Table 1. Intel® Pentium® 4 Processor Identification Information S-Spec SL4QD SL4SF 0F07h 0F07h 0F0Ah 0F0Ah 0F0Ah 0F0Ah 0F0Ah 0F0Ah 0F0Ah 0F0Ah 0F0Ah Speed Core/Bus Package and Revision 1.30GHz/400MHz 1.30GHz/400MHz 1.40GHz/400MHz - Intel BX80623I52500K | Specification Update - Page 25
Identification Information S-Spec SL4X4 SL57V SL4X5 SL5SX SL5VL SL5SY SL5VM SL5VN SL5SZ SL5UL SL5VM SL5WH SL5TQ SL59U SL59V SL5US SL59X SL5UT SL5VK SL5TG SL5TJ SL5VH SL5TK SL5VJ SL5VK SL5TL SL5N7 SL5N8 SL5UW SL5N9 SL5UV SL5UE SL5UF SL62Y Core L2 Cache Stepping Size (bytes) C1 256K C1 256K - Intel BX80623I52500K | Specification Update - Page 26
Identification Information S-Spec SL5UJ SL5UG SL62Z SL5UK SL5WG SL668 SL63X SL62P SL68Q SL68R SL5YR SL5YS SL68S SL68T SL5ZU SL65R SL67R SL683 SL67Y SL684 SL67Z SL685 SL682 SL6HL SL6K6 SL6LA SL6GQ SL6GR SL6DU SL6EF SL6DV SL6EG SL6DW SL6S6 Core L2 Cache Stepping Size (bytes) D0 256K D0 256K - Intel BX80623I52500K | Specification Update - Page 27
Identification Information S-Spec SL6S7 SL6S8 SL6RY SL6SR SL6S9 SL6RZ SL6SA SL6S2 SL6SB SL6S3 SL6S4 SL6S5 SL5TN SL4X5 SL6BC SL679 SL6BD SL67A SL6BE SL67B SL6BF SL67C SL6E7 SL6E8 SL6EE SL6E9 SL6SK SL6SL SL6K7 SL6SM Core L2 Cache Stepping Size (bytes) C1 512K C1 512K C1 512K C1 512K C1 - Intel BX80623I52500K | Specification Update - Page 28
Identification Information S-Spec SL6QN SL6QP SL6QQ SL6QR SL6Q7 SL6Q8 SL6Q9 SL6QA SL6QB SL6QC Core L2 Cache Stepping Size ( 0F29h 0F29h 0F29h 0F29h 0F29h 0F29h 0F29h 0F29h 0F29h 0F29h 0F29h 0F29h 0F29h Speed Core/Bus Package and Revision Notes 2.2GHz/400MHz 2.4GHz/400MHz 2.5GHz/400MHz 2.6GHz/ - Intel BX80623I52500K | Specification Update - Page 29
a boxed Intel® Pentium® 4 processor with an unattached fan heat sink. 2. These are tray processors, but some are also offered as boxed processors with an unattached fan heatsink. 3. These processors are Pentium 4 processors in the 423-pin package. 4. These processors are Pentium 4 processors in the - Intel BX80623I52500K | Specification Update - Page 30
These parts have multiple VIDs. 17. These parts will only operate at the specified core to bus frequency ratio and lower. 18. These parts have some specifications that differ from those in the Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Datasheet. The specifications that - Intel BX80623I52500K | Specification Update - Page 31
1. I/O Restart in SMM May Fail after Simultaneous Machine Check Exception (MCE). Problem: If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed, and if the data for this instruction becomes corrupted, the processor will signal a Machine Check Exception (MCE). If the - Intel BX80623I52500K | Specification Update - Page 32
0FFFh Requires a ModRM Byte Problem: Some invalid opcodes require a ModRM byte (or other following bytes), while others do not. The invalid opcode 0FFFh did not require a ModRM byte in previous generation Intel architecture processors, but does in the Pentium 4 processor. Implication: The use of - Intel BX80623I52500K | Specification Update - Page 33
ranges since the memory type has been translated to UC. Workaround: Intel does not support the overlapping of any two or more MTRRs unless one of them instruction after correcting the paging problem. Status: For the steppings affected, see the Summary Tables of Changes. 9. The Processor Signals - Intel BX80623I52500K | Specification Update - Page 34
fault in the page fault handler and then restart the faulting instruction. Status: For the steppings affected, see the Summary Tables of Changes. 10. IERR# May Not go Active When an Internal Error Occurs Problem: If the processor hangs because a store to the system bus does not complete, the - Intel BX80623I52500K | Specification Update - Page 35
of Memory Address Aliasing Problem: Aliasing refers to multiple logical addresses referencing the same physical address in memory. When multiple stores to the same physical memory location are pending in the processor, the processor must ensure that a subsequent instruction, which loads data from - Intel BX80623I52500K | Specification Update - Page 36
Instruction Register Shifting Problem: processor TAP has 7 opcode bits, it should shift out 0000001. The TAP stops driving on the same TAP clock edge that the receiver samples, with the result that 0000001 or 1000001 might be observed. Implication: The last bit may be incorrect during instruction - Intel BX80623I52500K | Specification Update - Page 37
. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 21. Processor May Hang on a Correctable Error and Snoop Combination Problem: The processor will hang whenever a Read-For-Ownership (RFO) or Locked-Read-ForOwnership (LRFO) hits a line in - Intel BX80623I52500K | Specification Update - Page 38
register. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 25. Processor May Fetch Reset Vector from Cache if A20M# Is Asserted during Init Problem: If A20M# is asserted with INIT# or after INIT# but before the first code fetch occurs, then - Intel BX80623I52500K | Specification Update - Page 39
will hang. Implication: When this erratum occurs, the processor will hang. Intel has not been able to reproduce this erratum with commercial steppings affected, see the Summary Tables of Changes. 29. Problem: REP MOV Instruction with Overlapping Source and Destination May Result in Data Corruption - Intel BX80623I52500K | Specification Update - Page 40
Summary Tables of Changes. 31. I/O Buffers for FERR#, PROCHOT# and THERMTRIP# Are Not AGTL+ Problem: The I/O buffers for the FERR#, PROCHOT# and THERMTRIP# signals are specified in the Intel® Pentium® 4 Processor in the 423-pin Package Datasheet as AGTL+ buffers. The buffers for these signals - Intel BX80623I52500K | Specification Update - Page 41
Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 34. Processor May Report Invalid TSS Fault Instead of Double Fault during Mode C Paging Problem: When an operating system executes a task switch via a Task State Segment (TSS) the CR3 register - Intel BX80623I52500K | Specification Update - Page 42
Summary Tables of Changes. 37. Debug Mechanisms May Not Function As Expected Problem: Certain debug mechanisms may not function as expected on the processor. The cases are as follows: When the following conditions occur: 1) An FLD instruction signals a stack overflow or underflow, 2) the FLD - Intel BX80623I52500K | Specification Update - Page 43
Problem: When the processor detects errors it should attempt to report and/or recover from the error. In the situations described below, the processor register, are not logged. • When one-half of a 64-byte instruction fetch from the L2 cache has an uncorrectable error and the other 32-byte - Intel BX80623I52500K | Specification Update - Page 44
may hang when an instruction code fetch receives a hard failure response from the system bus. This occurs because the bus control logic does not return data to the core, leaving the processor empty. IA32_MC0_STATUS MSR does indicate that a hard fail response occurred. • The processor may hang when - Intel BX80623I52500K | Specification Update - Page 45
: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 39. Processor May Timeout Waiting for a Device to Respond after 0.67 Seconds Problem: The PCI 2.1 target initial latency specification allows two seconds for a device to respond during initialization - Intel BX80623I52500K | Specification Update - Page 46
Is Available Problem: The processor should only processor register (IA32_THERM_CONTROL). The On-Demand Clock Modulation Duty Cycle is controlled by bits 3:1. If these bits are set to a duty cycle of 12.5% or 25%, the processor may hang while attempting to execute a floating-point instruction - Intel BX80623I52500K | Specification Update - Page 47
UC space and which takes an exception 16 (floating point error exception). The processor stalls trying to fetch the bytes of the faulting floating-point instruction and those following it. This processor hang is caused by interactions between thermal control circuit and floating-point event handler - Intel BX80623I52500K | Specification Update - Page 48
Problem: If the processor detects a page fault which is corrected before the operating system page fault handler can be called e.g., DMA activity modifies the page tables and the corrected page tables are left in a non-accessed or not dirty state, the processor may livelock. Intel instructions - Intel BX80623I52500K | Specification Update - Page 49
(WC) Load May Result in Unintended Address on System Bus Problem: When the processor performs a speculative write combining (WC) load, down the erratum occurs, an unintended load may be sent on system bus. Intel has only encountered this erratum during pre-silicon simulation. Workaround: It is - Intel BX80623I52500K | Specification Update - Page 50
Intel® Pentium® 4 Processor and Intel® 850 Chipset Platform Design Guide May Result in Loss of Cache Coherency Problem: When a Read for Ownership (RFO processor should recycle the RFO until the ECC error is handled. Due to this erratum, the processor does not recycle the RFO and attempts to service - Intel BX80623I52500K | Specification Update - Page 51
Processor Is in the System Management Mode (SMM), Debug Registers May Be Fully Writeable Problem: When in System Management Mode (SMM), the processor of at-retirement events that support precise-event-based sampling (PEBS). A number of performance metrics that support PEBS require a 2nd ESCR - Intel BX80623I52500K | Specification Update - Page 52
Stale Data following a Data, Address, or Response Parity Error Problem: If the processor experiences a data, address, or response parity error, the ADDRV the LSS instruction but the value of CR2 and the error code pushed on the stack are reflective of the speculative state. Intel has not observed - Intel BX80623I52500K | Specification Update - Page 53
(BRL) or Bus Read-Invalidate Line (BRIL) Problem: A processor internal cache fatal data ECC error may cause the processor to issue a BWL transaction to the same cache consumed leading to unpredictable program execution. Intel has not been able to reproduce this erratum with commercial software - Intel BX80623I52500K | Specification Update - Page 54
address. Status: For the steppings affected, see the Summary Tables of Changes. 64. Erroneous BIST Result Found in EAX Register after Reset Problem: The processor may show an erroneous BIST (built-in self test) result in the EAX register bit 0 after coming out of reset. Implication: When - Intel BX80623I52500K | Specification Update - Page 55
: For the steppings affected, see the Summary Tables of Changes. 67. CPUID Instruction Returns Incorrect Number of ITLB Entries Problem: When CPUID instruction is executed with EAX = 2 on a processor without HyperThreading Technology or with Hyper-Threading Technology disabled via power on - Intel BX80623I52500K | Specification Update - Page 56
Bytes Problem: If in a short window after an instruction Problem: If a locked operation accesses a line in the L1 cache that has a parity error, it is possible that the processor may hang while trying to evict the line. Implication: If this erratum occurs, it may result in a system hang. Intel - Intel BX80623I52500K | Specification Update - Page 57
and/or Application Hang or May Result in Incorrect Data Problem: On a small percentage of processors, a race condition exists in the power save logic of state without making forward progress, since the logical processor will not be able to service any pending event. This erratum has not been - Intel BX80623I52500K | Specification Update - Page 58
(RF Flag) in a Task-State Segment (TSS) May Be Incorrect Problem: After executing a JMP instruction to the next (or other) task through a hardware task switch, it of Changes. 78. Processor Provides a 4-Byte Store Unlock after an 8-Byte Load Lock Problem: When the processor is in the Page - Intel BX80623I52500K | Specification Update - Page 59
of the same instruction. It is possible for BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. 80. System Bus Interrupt Messages without Data Which Receive a HardFailure Response May Hang the Processor Problem: When a system - Intel BX80623I52500K | Specification Update - Page 60
processors is in the "Wait-for-SIPI" state, that logical processor will not have an MCE handler and will shut down and assert IERR#. Implication: A processor with a logical processor the #GP Exception Handler Problem: If a 16-bit application executes a branch instruction that causes an address - Intel BX80623I52500K | Specification Update - Page 61
Problem: The processor may temporarily hang in an HT Technology enabled system if one logical processor executes a synchronization loop that includes one or more locks and is waiting for release by the other logical processor. If the releasing logical processor is executing instructions - Intel BX80623I52500K | Specification Update - Page 62
is Chosen when On-Demand Clock Modulation is Enabled in a Processor Supporting Hyper-Threading Technology Problem: When a processor supporting Hyper-Threading Technology enables On-Demand Clock Modulation on both logical processors, the processor is expected to select the lowest duty cycle of the - Intel BX80623I52500K | Specification Update - Page 63
32 Intel® Architecture Software Developer's Manual, Volume Instruction Decoder Unit May Cause an Unpredictable Application Behavior and/or System Hang Problem: A timing marginality may exist in the clocking of the instruction a system hang. A processor supporting Hyper-Threading Technology may fail - Intel BX80623I52500K | Specification Update - Page 64
the Page Table Entry Problem: Under rare timing processor's Translation Lookaside Buffer (TLB) and used for memory operations. This erratum has not been observed with any commercially available software. Workaround: The guidelines in the IA-32 Intel® Architecture Software Developer's Manual - Intel BX80623I52500K | Specification Update - Page 65
Intel® Architecture Software Developer's Manual, Volume 3. Status: For the steppings affected, see the Summary Tables of Changes. 98. Brand String Field Reports Incorrect Maximum Operating Frequency on Intel® Pentium® 4 Extreme Edition Processor with 1066 MHz FSB Problem: Pentium 4 processor - Intel BX80623I52500K | Specification Update - Page 66
Write) Transaction Problem: Under limited circumstances, the processors may, after Instruction with Fast Strings Enabled Problem: Under limited circumstances while executing a REP MOVS/STOS string instruction an architectural page fault is signaled. Intel has not observed this erratum with - Intel BX80623I52500K | Specification Update - Page 67
the vector will be left set in the in-service register and mask all interrupts at the same or Is Asserted May Result in Incorrect Address Translations Problem: An external A20M# pin if enabled forces loads to be observed out of order. Intel has not observed this erratum with any commercially - Intel BX80623I52500K | Specification Update - Page 68
Breakpoint Condition Detected Flags May be set Incorrectly Problem: The Debug Status Register (DR6) may report detection of a spurious breakpoint condition under certain boundary conditions when either: • A "MOV SS" or "POP SS" instruction is immediately followed by a hardware debugger breakpoint - Intel BX80623I52500K | Specification Update - Page 69
423-pin Package, Intel® Pentium® 4 Processor in the 478-pin Package Datasheet • Intel® Pentium® 4 Processor in the 478-pin Package Datasheet • Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process and Intel® Pentium® 4 Processor Extreme Edition Supporting Hyper-Threading Technology - Intel BX80623I52500K | Specification Update - Page 70
Guide, the Time Stamp Counter definition has been updated to include support for the future processors. This change will be incorporated in the next revision of the IA-32 Intel® Architecture Software Developer's Manual. 15.8 TIME-STAMP COUNTER The IA-32 architecture (beginning with the Pentium - Intel BX80623I52500K | Specification Update - Page 71
To determine average processor clock frequency, Intel recommends the use of Performance Monitoring logic to count processor core clocks over the period of time for which the average is required. See Section 15.10.9 and Appendix A in this manual for more information. The RDTSC instruction reads the - Intel BX80623I52500K | Specification Update - Page 72
ratios like cycles per instruction (CPI). Processor clocks may stop ticking under circumstances like the following: • The processor is halted when there is nothing for the CPU to do. For example, the processor may halt to save power while the computer is servicing an I/O request. When Hyper - Intel BX80623I52500K | Specification Update - Page 73
Specification Clarifications § Specification Update 73 - Intel BX80623I52500K | Specification Update - Page 74
423-pin Package, Intel® Pentium® 4 Processor in the 478-pin Package Datasheet • Intel® Pentium® 4 Processor in the 478-pin Package Datasheet • Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process and Intel® Pentium® 4 Processor Extreme Edition Supporting Hyper-Threading Technology
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Intel
®
Pentium
®
4 Processor
Specification Update
August 2008
Revision 071
Document Number:
249199-071