Intel E5440 Data Sheet

Intel E5440 - Cpu Xeon Quad Core 2.83Ghz Fsb1333Mhz 12M Lga771 Tray Manual

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  • Intel E5440 | Data Sheet - Page 1
    Quad-Core Intel® Xeon® Processor 5400 Series Datasheet August 2008 318589-005
  • Intel E5440 | Data Sheet - Page 2
    of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Quad-Core Intel® Xeon® Processor 5400 Series may contain
  • Intel E5440 | Data Sheet - Page 3
    Handling Guidelines 48 3.5 Package Insertion Specifications 48 3.6 Processor Mass Specifications 48 3.7 Processor Materials 48 3.8 Processor Markings 48 3.9 Processor Land Coordinates 49 4 Land Listing...51 4.1 Quad-Core Intel® Xeon® Processor 5400 Series Pin Assignments 51 4.1.1 Land Listing
  • Intel E5440 | Data Sheet - Page 4
    Processor Heat Sink Weight 113 8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK 113 8.3 Electrical Requirements 113 8.3.1 Fan Power Supply (Active CEK 113 8.3.2 Boxed Processor Cooling Requirements 114 8.4 Boxed Processor 118 4 Quad-Core Intel® Xeon® Processor 5400 Series
  • Intel E5440 | Data Sheet - Page 5
    Hysteresis 25 2-2 Quad-Core Intel® Xeon® Processor X5482 Load Current versus Time 30 2-3 Quad-Core Intel® Xeon® Processor X5400 Series Load Current versus Time 31 2-4 Quad-Core Intel® Xeon® Processor E5400 Series Load Current versus Time 31 2-5 Quad-Core Intel® Xeon® Processor L5400 Series Load
  • Intel E5440 | Data Sheet - Page 6
    27 2-12 Voltage and Current Specifications 28 2-13 Quad-Core Intel® Xeon® Processor X5482 VCC Static and Transient Tolerance 32 2-14 Quad-Core Intel® Xeon® Processor X5400 Series, Quad-Core Intel® Xeon® Processor E5400 Series, Quad-Core Intel® Xeon® Processor L5400 Series VCC Static and Transient
  • Intel E5440 | Data Sheet - Page 7
    002 003 004 005 Description Initial release Added product information for the Quad-Core Intel® Xeon® Processor L5408. Added product information for the Quad-Core Intel® Xeon® Processor L5400 Series. Corrected L1 cache size Introduced X5492 Updated X5482 power levels on E-step Maintains change bars
  • Intel E5440 | Data Sheet - Page 8
    8 Quad-Core Intel® Xeon® Processor 5400 Series Datasheet
  • Intel E5440 | Data Sheet - Page 9
    1 Introduction The Quad-Core Intel® Xeon® Processor 5400 Series is a server/workstation processor utilizing four 45-nm Hi-k next generation Intel® Core™ microarchitecture cores. The processor is manufactured on Intel's 45 nanometer process technology combining high performance with the power
  • Intel E5440 | Data Sheet - Page 10
    power delivery. It utilizes a surface mount LGA771 socket that supports Direct Socket Loading (DSL). Table 1-1. Quad-Core Intel® Xeon® Processor 5400 Series # of Processor Cores L1 Cache 4 32 KB instruction per core 32 KB data per core L2 Advanced Cache 2x6 MB shared Front Side Bus Frequency
  • Intel E5440 | Data Sheet - Page 11
    SKU. • Quad-Core Intel® Xeon® Processor L5408 - Intel 64-bit microprocessor intended for dual processor server blades and embedded servers. The Quad-Core Intel® Xeon® Processor L5408 is a lower voltage and lower power version of the Quad-Core Intel® Xeon® Processor 5400 Series supporting higher case
  • Intel E5440 | Data Sheet - Page 12
    buses, rather than a processor bus shared between two processor agents. The DIB architecture provides improved performance by allowing increased FSB speeds and bandwidth. • Flexible Motherboard Guidelines (FMB) - Estimate of the maximum values the Quad-Core Intel® Xeon® Processor 5400 Series will
  • Intel E5440 | Data Sheet - Page 13
    Voltage Regulator-Down (EVRD) 11.0 Design Guidelines Quad-Core Intel® Xeon® Processor 5400 Series Thermal/Mechanical Design Guidelines (TMDG) LGA771 Socket Mechanical Design Guide 315889 318611 313871 Quad-Core Intel® Xeon® Processor 5400 Series Boundary Scan Descriptive Language (BSDL) Model
  • Intel E5440 | Data Sheet - Page 14
    14
  • Intel E5440 | Data Sheet - Page 15
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 2 Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 2.1 Front Side Bus and GTLREF Most Quad-Core Intel® Xeon® Processor 5400 Series FSB signals use Assisted Gunning Transceiver Logic (AGTL+) signaling
  • Intel E5440 | Data Sheet - Page 16
    and high internal clock speeds, the Quad-Core Intel® Xeon® Processor 5400 Series is capable of generating regulator (EVRD or VRM pins) to the LGA771 socket. Bulk decoupling must be provided on the baseboard the expected load. To insure optimal performance, various factors associated with the power
  • Intel E5440 | Data Sheet - Page 17
    are not necessarily committed production frequencies. 3. For valid processor core frequencies, see Quad-Core Intel® Xeon® Processor 5400 Series Specification Update. 4. The lowest bus ratio supported by the Quad-Core Intel® Xeon® Processor 5400 Series is 1/6. 2.4.1 Front Side Bus Frequency Select
  • Intel E5440 | Data Sheet - Page 18
    VID settings. This is reflected by the VID range values provided in Table 2-3. The Quad-Core Intel® Xeon® Processor 5400 Series uses six voltage identification signals, VID[6:1], to support automatic selection of power supply voltages. Table 2-3 specifies the voltage level corresponding to the
  • Intel E5440 | Data Sheet - Page 19
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications The Quad-Core Intel® Xeon® Processor 5400 Series provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (VCC). This will represent a DC shift in the load line. It should
  • Intel E5440 | Data Sheet - Page 20
    "111111" VID pattern is observed, the voltage regulator output should be disabled. 2. Shading denotes the expected VID range of the Quad-Core Intel® Xeon® Processor 5400 Series. 3. The VID range includes VID transitions that may be initiated by thermal events, assertion of the FORCEPR# signal (see
  • Intel E5440 | Data Sheet - Page 21
    Truth Table for MS_ID[1:0] MS_ID1 0 0 1 1 MS_ID0 0 1 0 1 Description Dual-Core Intel® Xeon® Processor 5200 Series Dual-Core Intel® Xeon® Processor 5100 series Quad-Core Intel® Xeon® Processor 5300 series Quad-Core Intel® Xeon® Processor 5400 Series Note: The MS_ID[1:0] signals are provided to
  • Intel E5440 | Data Sheet - Page 22
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications The TESTHI signals must use [2:1]# ADS#, AP[1:0]#, BINIT#2, BNR#2, BPM5#, BPM3#, BPM0#,BPMb3#, BPMb0#, BR[1:0]#, DBSY#, DP[3:0]#, DRDY#, HIT#2, HITM#2, LOCK#, MCERR#2 Signals Associated Strobe REQ[4:0]#,A[16:3]#, ADSTB0# A[37:
  • Intel E5440 | Data Sheet - Page 23
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-6. FSB Signal Groups ( :3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, BNR#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY
  • Intel E5440 | Data Sheet - Page 24
    Interface (PECI) DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The Quad-Core Intel® Xeon® Processor 5400 Series contains Digital Thermal Sensor (DTS
  • Intel E5440 | Data Sheet - Page 25
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-10. PECI DC Electrical must use a Schmitt-triggered input design for improved noise immunity. Use Figure 2-1 as a guide for input buffer design. Figure 2-1. Input Device Hysteresis VTT Maximum VP Minimum VP Maximum VN
  • Intel E5440 | Data Sheet - Page 26
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 2.11 Note: 2.12 Mixing Processors Intel supports and validates dual processor configurations only in which both processors operate with the same FSB frequency, core frequency, power segments, and have the same internal cache
  • Intel E5440 | Data Sheet - Page 27
    be taken to read all notes associated with each parameter. 2.13.1 Flexible Motherboard Guidelines (FMB) The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the Quad-Core Intel® Xeon® Processor 5400 Series will have over certain time periods. The values are only estimates
  • Intel E5440 | Data Sheet - Page 28
    ICC for Quad-Core Intel® Xeon® Processor E5400 Series with multiple VID Launch - FMB ICC for Quad-Core Intel® Xeon® Processor L5400 Series with multiple VID Launch - FMB ICC for Quad-Core Intel® Xeon® Processor L5408 with multiple VID Launch - FMB ICC_RESET for Quad-Core Intel® Xeon® Processor X5482
  • Intel E5440 | Data Sheet - Page 29
    TDC) Quad-Core Intel® Xeon® Processor X5482 Launch - FMB Thermal Design Current (TDC) Quad-Core Intel® Xeon® Processor X5400 Series Launch - FMB Thermal Design Current (TDC) Quad-Core Intel® Xeon® Processor E5400 Series Launch - FMB Thermal Design Current (TDC) Quad-Core Intel® Xeon® Processor L5400
  • Intel E5440 | Data Sheet - Page 30
    details on the average processor current draw over various time durations. 6. FMB is the flexible motherboard guideline. These guidelines are asserted. 18. The Quad-Core Intel® Xeon® Processor X5482 is intended for dual processor workstations only. Quad-Core Intel® Xeon® Processor X5482 Load Current
  • Intel E5440 | Data Sheet - Page 31
    circuitry should not trip for load currents greater than ICC_TDC. 2. Not 100% tested. Specified by design characterization. Figure 2-4. Quad-Core Intel® Xeon® Processor E5400 Series Load Current versus Time Sustained Current (A) 10 5 10 0 95 90 85 80 75 0 .0 1 0 .1 1 10 10 0 10
  • Intel E5440 | Data Sheet - Page 32
    thermal protection circuitry should not trip for load currents greater than ICC_TDC. 2. Not 100% tested. Specified by design characterization. Table 2-13. Quad-Core Intel® Xeon® Processor X5482 VCC Static and Transient Tolerance (Sheet 1 of 2) ICC (A) 0 5 10 15 20 25 30 35 40 45 50 55 60 65
  • Intel E5440 | Data Sheet - Page 33
    Guidelines for socket load line guidelines and VR implementation. Please refer to the appropriate platform design guide for details on VR implementation. Table 2-14. Quad-Core Intel® Xeon® Processor X5400 Series, Quad-Core Intel® Xeon® Processor E5400 Series, Quad-Core Intel® Xeon® Processor L5400
  • Intel E5440 | Data Sheet - Page 34
    (EVRD) 11.0 Design Guidelines for socket load line guidelines and VR implementation. Please refer to the appropriate platform design guide for details on VR implementation. 4. ICC values greater than 102A are not applicable for the Quad-Core Intel® Xeon® Processor E5400 Series. 5. ICC values greater
  • Intel E5440 | Data Sheet - Page 35
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-7. Quad-Core Intel® Xeon® Processor X5482 VCC Static and Transient Tolerance Load Lines 0 VID - 0.000 Icc [A] 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75
  • Intel E5440 | Data Sheet - Page 36
    060 VCC Maximum VID - 0.080 VID - 0.100 VID - 0.120 VID - 0.140 VID - 0.160 VCC Minimum VCC Typical VID - 0.180 VID - 0.200 Figure 2-9. Quad-Core Intel® Xeon® Processor E5400 Series VCC Static and Transient Tolerance Load Lines Vcc [V] 0 VID - 0.000 Icc [A] 5 10 15 20 25 30 35 40 45 50 55
  • Intel E5440 | Data Sheet - Page 37
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-10. Quad-Core Intel® Xeon® Processor L5400 Series VCC Static and Transient Design Guidelines for socket load line guidelines and VR implementation. Please refer to the appropriate platform design guide for details on
  • Intel E5440 | Data Sheet - Page 38
    by value of the external pullup resistor to VTT. Refer to platform design guide for details. 4. For VIN between 0 V and VOH. 2.13.2 VCC Overshoot Specification The Quad-Core Intel® Xeon® Processor 5400 Series can tolerate short transient overshoot events where VCC exceeds the VID voltage
  • Intel E5440 | Data Sheet - Page 39
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-11. VCC Overshoot Example Waveform VID + 0.050 oscilloscope. 2.14 AGTL+ FSB Specifications Routing topologies are dependent on the processors supported and the chipset used in the design. Please refer to the
  • Intel E5440 | Data Sheet - Page 40
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications The AGTL+ reference voltages ( be provided on the system board with 1% resistors. See the applicable platform design guide for implementation details. Table 2-20. FSB Differential BCLK Specifications Symbol VL VH VCROSS(
  • Intel E5440 | Data Sheet - Page 41
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input
  • Intel E5440 | Data Sheet - Page 42
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-14. Differential Clock Crosspoint Specification Crossing Point (mV) 650 600 550 500 550 + 0.5 (VHavg - 700) 450 550 mV 400 250 + 0.5 (
  • Intel E5440 | Data Sheet - Page 43
    Mechanical Specifications 3 Mechanical Specifications The Quad-Core Intel® Xeon® Processor 5400 Series is packaged in a Flip Chip Land Grid Array (FC-LGA) package that interfaces to the baseboard via a LGA771 socket. The package consists of a processor core mounted on a pinless substrate with 771
  • Intel E5440 | Data Sheet - Page 44
    Mechanical Specifications Figure 3-2. Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing (Sheet 1 of 3) Note: Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution are available in the processor Thermal/Mechanical Design
  • Intel E5440 | Data Sheet - Page 45
    Mechanical Specifications Figure 3-3. Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing (Sheet 2 of 3) 45
  • Intel E5440 | Data Sheet - Page 46
    Mechanical Specifications Figure 3-4. Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing (Sheet 3 of 3) Note: The optional dimple packing marking highlighted by Detail F from the above drawing may only be found on initial processors. 46
  • Intel E5440 | Data Sheet - Page 47
    bend limits, please refer to the MAS document titled Manufacturing with Intel® components using 771-land LGA package that interfaces with the motherboard via a LGA771 socket. 9. Refer to the Quad-Core Intel® Xeon® Processor 5400 Series Thermal/Mechanical Design Guidelines (TMDG)for information on
  • Intel E5440 | Data Sheet - Page 48
    LGA771 Socket Design Guidelines. 3.6 Processor Mass Specifications The typical mass of the Quad-Core Intel® Xeon® Processor 5400 Series is 21.5 grams [0.76 oz.]. This includes all components which make up the entire processor product. 3.7 Processor Materials The Quad-Core Intel® Xeon® Processor
  • Intel E5440 | Data Sheet - Page 49
    GROUP1LINE3 GROUP1LINE4 GROUP1LINE5 Mark Text (Production Mark): 3200DP/12M/1600 Intel ® Xeon ® Proc# SXXX COO i (M) © '07 FPO ATPO S/N Note: 2D matrix is required for engineering samples only (encoded with ATPO-S/N). 3.9 Processor Land Coordinates Figure 3-6 and Figure 3-7 show the top and
  • Intel E5440 | Data Sheet - Page 50
    Mechanical Specifications Figure 3-7. Processor Land Coordinates, Bottom View AN AM AL AK AJ AH AG AF AE AD AC AB AA Address / 25 26 27 28 29 30 AN AM AL AK AJ AH AG AF AE AD AC AB AA Y Socket 771 W V Quadrants U T Bottom View R P N M L K J H G F E D
  • Intel E5440 | Data Sheet - Page 51
    Listing 4 Land Listing 4.1 Quad-Core Intel® Xeon® Processor 5400 Series Pin Assignments This section provides sorted land list in Table 4-1 and Table 4-2. Table 4-1 is a listing of all processor lands ordered alphabetically by land name. Table 4-2 is a listing of all processor lands ordered by
  • Intel E5440 | Data Sheet - Page 52
    Land Listing Table 4-1. Land Listing by Land Name (Sheet 3 of 20) Pin Name BSEL0 BSEL1 BSEL2 COMP0 COMP1 COMP2 COMP3 D00# D01# D02# D03# D04# D05# D06# D07# D08# D09# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# Pin No. Signal
  • Intel E5440 | Data Sheet - Page 53
    Land Listing Table 4-1. Land Listing by Land Name (Sheet 5 of 20) Pin Name Pin No. Signal Buffer Type Direction DP2# H16 DP3# J17 DRDY# C1 DSTBN0# C8 DSTBN1# G12 DSTBN2# G20 DSTBN3# A16 DSTBP0# B9 DSTBP1# E12 DSTBP2# G19 DSTBP3# C17 FERR#/PBE# R3 FORCEPR# AK6
  • Intel E5440 | Data Sheet - Page 54
    Land Listing Table 4-1. Land Listing by Land Name (Sheet 7 of 20) Pin Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESET# RS0# RS1# RS2# RSP# SKTOCC# SMI# STPCLK# TCK TDI TDO TESTHI10 TESTHI11 TESTHI12 TESTIN1 TESTIN2 THERMTRIP# TMS TRDY# TRST# VCC VCC VCC VCC VCC VCC VCC
  • Intel E5440 | Data Sheet - Page 55
    Land Listing Table 4-1. Land Listing by Land Name (Sheet 9 of 20) Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin Signal Buffer No. Type AG30 AG8 AG9 AH11 AH12 AH14 AH15
  • Intel E5440 | Data Sheet - Page 56
    Land Listing Table 4-1. Land Listing by Land Name (Sheet 11 of 20) Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin Signal Buffer No. Type AN8 AN9 J10 J11 J12 J13 J14 J15
  • Intel E5440 | Data Sheet - Page 57
    Land Listing Table 4-1. Land Listing by Land Name (Sheet 13 of 20) Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC_DIE_SENSE VCC_DIE_SENSE2 VCCPLL VID_SELECT VID1 VID2 VID3 VID4 VID5 VID6 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin No. Signal Buffer
  • Intel E5440 | Data Sheet - Page 58
    Land Listing Table 4-1. Land Listing by Land Name (Sheet 15 of 20) Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Signal Buffer No. Type AF29 AF3 AF30 AF6 AG10 AG13
  • Intel E5440 | Data Sheet - Page 59
    Land Listing Table 4-1. Land Listing by Land Name (Sheet 17 of 20) Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Signal Buffer No. Type B11 B14 B17 B20 B24 B5 B8 C10
  • Intel E5440 | Data Sheet - Page 60
    Land Listing Table 4-1. Land Listing by Land Name (Sheet 19 of 20) Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Signal Buffer No. Type L7 Power/Other M1 Power/
  • Intel E5440 | Data Sheet - Page 61
    Land Listing 4.1.2 Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 1 of 20) Pin No. Pin Name A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A2 A20 A21 A22 A23 A24 A25 A26 A3 A4 A5 A6 A7 A8 A9 AA1 AA2 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA3 AA30 AA4 AA5 AA6 D08# D09# VSS COMP0
  • Intel E5440 | Data Sheet - Page 62
    Land Listing Table 4-2. Land Listing by Land Number (Sheet 3 of 20) Pin No. Pin Name AD26 AD27 AD28 AD29 AD3 AD30 AD4 AD5 AD6 AD7 AD8 AE1 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE2 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE3 AE30 AE4 AE5 AE6 AE7 AE8 VCC VCC VCC VCC BINIT#
  • Intel E5440 | Data Sheet - Page 63
    Land Listing Table 4-2. Land Listing by Land Number (Sheet 5 of 20) Pin No. Pin Name AG18 AG19 AG2 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG3 AG30 AG4 AG5 AG6 AG7 AG8 AG9 AH1 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH2 AH20 AH21 AH22 AH23 AH24 AH25 AH26 VCC VCC BPM3# VSS VCC
  • Intel E5440 | Data Sheet - Page 64
    Land Listing Table 4-2. Land Listing by Land Number (Sheet 7 of 20) Pin No. Pin Name AJ9 AK1 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK2 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK3 AK30 AK4 AK5 AK6 AK7 AK8 AK9 AL1 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 VCC RESERVED VSS VCC
  • Intel E5440 | Data Sheet - Page 65
    Land Listing Table 4-2. Land Listing by Land Number (Sheet 9 of 20) Pin No. Pin Name AM26 AM27 AM28 AM29 AM3 AM30 AM4 AM5 AM6 AM7 AM8 AM9 AN1 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN2 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN3 AN4 AN5 AN6 AN7 AN8 AN9 B1 VCC VSS VSS VCC VID2 VCC VSS VID6
  • Intel E5440 | Data Sheet - Page 66
    Land Listing Table 4-2. Land Listing by Land Number (Sheet 11 of 20) Pin No. Pin Name C2 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C3 C30 C4 C5 C6 C7 C8 C9 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 D21 D22 D23 D24 D25 D26 D27 D28 BNR# DBI3# D58# VSS RESERVED VSS VTT VTT VTT VTT VTT LOCK#
  • Intel E5440 | Data Sheet - Page 67
    Land Listing Table 4-2. Land Listing by Land Number (Sheet 13 of 20) Pin No. Pin Name Signal Buffer Type Direction F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F2 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F3 F30 F4 F5 F6 F7 F8 F9 G1 G10 G11 G12 G13 G14 G15 G16 G17 G18 VSS D23# D24# VSS D28# D30# VSS
  • Intel E5440 | Data Sheet - Page 68
    Land Listing Table 4-2. Land Listing by Land Number (Sheet 15 of 20) Pin No. Pin Name H27 H28 H29 H3 H30 H4 H5 H6 H7 H8 H9 J1 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J2 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J3 J30 J4 J5 J6 J7 J8 VSS VSS VSS VSS BSEL1 RSP# BR1# VSS VSS VSS VSS VTT_OUT VCC VCC
  • Intel E5440 | Data Sheet - Page 69
    Land Listing Table 4-2. Land Listing by Land Number (Sheet 17 of 20) Pin No. Pin Name M28 M29 M3 M30 M4 M5 M6 M7 M8 N1 N2 N23 N24 N25 N26 N27 N28 N29 N3 N30 N4 N5 N6 N7 N8 P1 P2 P23 P24 P25 P26 P27 P28 P29 P3 P30 P4 P5 P6 P7 VCC VCC STPCLK# VCC A07# A03# REQ2# VSS VCC PWRGOOD IGNNE# VCC VCC VCC
  • Intel E5440 | Data Sheet - Page 70
    Land Listing Table 4-2. Land Listing by Land Number (Sheet 19 of 20) Pin No. Pin Name U28 U29 U3 U30 U4 U5 U6 U7 U8 V1 V2 V23 V24 V25 V26 V27 V28 V29 V3 V30 V4 V5 V6 V7 V8 W1 W2 W23 W24 W25 W26 W27 W28 W29 W3 W30 W4 W5 W6 W7 VCC VCC AP1# VCC A13# A12# A10# VSS VCC MS_ID1 LL_ID0 VSS VSS VSS VSS
  • Intel E5440 | Data Sheet - Page 71
    processor's address wrap- around at the 1 MB boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction pins of all Quad-Core Intel® Xeon® Processor 5400 Series FSB agents
  • Intel E5440 | Data Sheet - Page 72
    refer to the appropriate platform design guidelines for more detailed information. I/O BPMb[3:0]# (Breakpoint Monitor) are breakpoint and performance O monitor signals. They are outputs from the processor which indicate I/O the status of breakpoints and programmable counters used for monitoring
  • Intel E5440 | Data Sheet - Page 73
    in-target probe can drive system reset. If a debug port connector is implemented in the system, DBR# is a noconnect on the Quad-Core Intel® Xeon® Processor 5400 Series package. DBR# is not a processor signal. I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for 3 driving data on the
  • Intel E5440 | Data Sheet - Page 74
    and IA-32 Architectures Software Developer's Manual and the Intel Processor Identification and the CPUID Instruction application note. I The FORCEPR# (force power reduction) input can be used by the platform to cause the Quad-Core Intel® Xeon® Processor 5400 Series to activate the Thermal Control
  • Intel E5440 | Data Sheet - Page 75
    signal following an I/O write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O write bus transaction. I INIT# (Initialization), when asserted, resets integer registers inside 2 all processors without affecting their internal caches or floating-point registers
  • Intel E5440 | Data Sheet - Page 76
    Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3. O These signals are provided to indicate the Market Segment for the processor and may be used for future processor signal resets all processors to known states 3 and invalidates their internal caches without writing back any
  • Intel E5440 | Data Sheet - Page 77
    its internal clocks (thus halting program execution) in an attempt to reduce the processor junction temperature. To protect the processor its core voltage (VCC) must be removed following the assertion of THERMTRIP#. Intel also recommends the removal of VTT when THERMTRIP# is asserted. Driving of
  • Intel E5440 | Data Sheet - Page 78
    to VTT on the motherboard. O The VTT_SEL signal is used to select the correct VTT voltage level for the processor. VTT_SEL is connected to VSS on the Quad-Core Intel® Xeon® Processor 5400 Series package. Notes: 1. For this processor land on the Quad-Core Intel® Xeon® Processor 5400 Series, the
  • Intel E5440 | Data Sheet - Page 79
    Guidelines (TMDG) or Quad-Core Intel® Xeon® Processor L5408 Series in Embedded Applications Thermal/Mechanical Design Guidelines (TMDG). The Quad-Core Intel® Xeon® Processor 5400 Series implements a methodology for managing processor temperatures which is intended to support acoustic noise reduction
  • Intel E5440 | Data Sheet - Page 80
    to guarantee the case temperature meets the thermal profile specifications. The Quad-Core Intel® Xeon® Processor X5482, and Quad-Core Intel® Xeon® Processor E5400 Series, and Quad-Core Intel® Xeon® Processor L5400 Series support a single Thermal Profile (see Figure 6-1, and Figure 6-3 and Figure
  • Intel E5440 | Data Sheet - Page 81
    . TDP is measured at maximum TCASE. 3. These specifications are based on silicon characterization. 4. Power specifications are defined at all VIDs found in Table 2-3. The Quad-Core Intel® Xeon® Processor X5482 may be shipped under multiple VIDs for each frequency. 5. FMB, or Flexible Motherboard
  • Intel E5440 | Data Sheet - Page 82
    Thermal Specifications Table 6-2. Quad-Core Intel® Xeon® Processor X5492 and X5482 (C-step)Thermal Profile Table Power (W) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
  • Intel E5440 | Data Sheet - Page 83
    Table 2-3. The Quad-Core Intel® Xeon® Processor X5400 Series may be shipped under multiple VIDs for each frequency. 5. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements. Figure 6-2. Quad-Core Intel® Xeon® Processor X5400 Series
  • Intel E5440 | Data Sheet - Page 84
    Thermal Specifications Table 6-4. Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profile A Table Power (W) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
  • Intel E5440 | Data Sheet - Page 85
    Power (TDP) should be used for the processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is The Quad-Core Intel® Xeon® Processor E5400 Series may be shipped under multiple VIDs for each frequency. 5. FMB, or Flexible Motherboard, guidelines
  • Intel E5440 | Data Sheet - Page 86
    will result in increased probability of TCC activation and may incur measurable performance loss. (See Section 6.2 for details on TCC activation). 3. Refer to the Quad-Core Intel® Xeon® Processor 5400 Series Thermal/Mechanical Design Guidelines (TMDG) for system and environmental implementation
  • Intel E5440 | Data Sheet - Page 87
    or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements. Figure 6-4. Quad-Core Intel® Xeon® Processor L5400 measurable performance loss. (See Section 6.2 for details on TCC activation). 3. Refer to the Quad-Core Intel® Xeon® Processor
  • Intel E5440 | Data Sheet - Page 88
    Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is 2-12. The Quad-Core Intel® Xeon® Processor L5408 may be shipped under multiple VIDs for each frequency. 5. FMB, or Flexible Motherboard, guidelines provide
  • Intel E5440 | Data Sheet - Page 89
    of the Quad-Core Intel® Xeon® Processor L5408 Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss
  • Intel E5440 | Data Sheet - Page 90
    and is for reference only. Processor Thermal Features Intel® Thermal Monitor Features Quad-Core Intel® Xeon® Processor 5400 Series provides two thermal monitor features, Intel® Thermal Monitor 1 and Intel® Thermal Monitor 2. The Intel® Thermal Monitor 1 and Intel® Thermal Monitor 2 must both be
  • Intel E5440 | Data Sheet - Page 91
    will support Intel® Thermal Monitor 2 will be provided in future releases of the Quad-Core Intel® Xeon® Processor 5400 Series Thermal/Mechanical Design Guidelines (TMDG) when available. For more details also refer to the Intel® 64 and IA-32 Architectures Software Developer's Manual. When Intel
  • Intel E5440 | Data Sheet - Page 92
    lowest supported bus ratio (1/6 for the Quad-Core Intel® Xeon® Processor 5400 Series). When the TCC is activated, the processor automatically transitions to the new frequency. This transition occurs rapidly, on the order of 5 µs. During the frequency transition, the processor is unable to service
  • Intel E5440 | Data Sheet - Page 93
    measurements of TCASE, or PROCHOT#. FORCEPR# Signal The FORCEPR# (force power reduction) input can be used by the platform to cause the Quad-Core Intel® Xeon® Processor 5400 Series to activate the TCC. If the Thermal Monitor is enabled, the TCC will be activated upon the assertion of the FORCEPR
  • Intel E5440 | Data Sheet - Page 94
    to 2Mbps). The PECI interface on the Quad-Core Intel® Xeon® Processor 5400 Series is disabled by default and must be enabled through BIOS. Figure 6-8. Quad-Core Intel® Xeon® Processor 5400 Series PECI Topology P ro c es s o r (Socket 0) 0 x 3 D om ain0 G5 0 0 x 3 D om ain1 0 PECI Host
  • Intel E5440 | Data Sheet - Page 95
    settling on a fan control algorithm are the DTS sample rate, whether the temperature filter is enabled, how often the PECI host will poll the processor for temperature data, and the rate at which fan speed is changed. Depending on the designer's specific requirements the DTS sample rate and alpha
  • Intel E5440 | Data Sheet - Page 96
    PECI device address for socket 0 is 0x30 and socket 1 is 0x31. Please note that each address also supports two domains (Domain0 condition. 6.3.2.4 PECI GetTemp0() and GetTemp1() Error Code Support The error codes supported for the processor GetTemp0() and GetTemp1() commands are listed in Table
  • Intel E5440 | Data Sheet - Page 97
    EXT_CONFIG Model Specific Register (MSR). This MSR will allow for the disabling of a single core per die within the package. 7.2 Clock Control and Low Power States The Quad-Core Intel® Xeon® Processor 5400 Series supports the Extended HALT state (also referred to as C1E) in addition to the HALT
  • Intel E5440 | Data Sheet - Page 98
    Extended HALT state requires support for dynamic VID transitions in the platform. HALT State HALT is a low power state entered when the processor have executed the HALT or MWAIT instruction. When one of the processor cores execute the HALT or MWAIT instruction, that processor core is halted; however
  • Intel E5440 | Data Sheet - Page 99
    PEXTENDED_HALT Quad-Core Intel® Xeon® Processor L5408 Extended HALT State Power Extended HALT State Power Extended HALT State Power Extended HALT State Power Typ Max 16 Unit W Notes 1 2 16 W 2 16/20 W 2,3 12 W 2 12 W 4 Notes: 1. Processors running in the lowest bus ratio supported
  • Intel E5440 | Data Sheet - Page 100
    Service snoops to caches 7.2.3 100 Stop-Grant State When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered no later than 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle. By default, the Quad-Core Intel® Xeon
  • Intel E5440 | Data Sheet - Page 101
    Software Developer's Manual. Not all Quad-Core Intel® Xeon® Processor 5400 Series are capable of supporting Enhanced Intel SpeedStep Technology. More details on which processor frequencies will support this feature will be provided in the Quad-Core Intel® Xeon® Processor 5400 Series Specification
  • Intel E5440 | Data Sheet - Page 102
    by changing the bus to core frequency ratio and voltage. This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system. The Quad-Core Intel® Xeon® Processor 5400 Series has hardware logic that coordinates
  • Intel E5440 | Data Sheet - Page 103
    heatsink. Quad-Core Intel® Xeon® Processor E5400 Series and Quad-Core Intel® Xeon® Processor L5400 Series with 80W and lower TDPs will include acoustic targets in pedestal platforms through the motherboards's ability to directly control the RPM of the processor heat sink fan. See Section 8.3 for
  • Intel E5440 | Data Sheet - Page 104
    Boxed Processor Specifications Figure 8-1. Boxed Quad-Core Intel® Xeon® Processor 5400 Series 1U Passive/3U+ Active Combination Heat Sink (With Removable Fan) Figure 8-2. Boxed Quad-Core Intel® Xeon® Processor 5400 Series 2U Passive Heat Sink 104
  • Intel E5440 | Data Sheet - Page 105
    Specifications Figure 8-3. 2U Passive Quad-Core Intel® Xeon® Processor 5400 Series Thermal Solution (Exploded View) 8.2 8.2.1 Notes: 1. The heat sinks represented in these images are for reference only, and may not represent the final boxed processor heat sinks. 2. The screws, springs, and
  • Intel E5440 | Data Sheet - Page 106
    Figure 8-4. Top Side Board Keepout Zones (Part 1) Boxed Processor Specifications 106
  • Intel E5440 | Data Sheet - Page 107
    Boxed Processor Specifications Figure 8-5. Top Side Board Keepout Zones (Part 2) 107
  • Intel E5440 | Data Sheet - Page 108
    Figure 8-6. Bottom Side Board Keepout Zones Boxed Processor Specifications 108
  • Intel E5440 | Data Sheet - Page 109
    Boxed Processor Specifications Figure 8-7. Board Mounting-Hole Keepout Zones 109
  • Intel E5440 | Data Sheet - Page 110
    Figure 8-8. Volumetric Height Keep-Ins Boxed Processor Specifications 110
  • Intel E5440 | Data Sheet - Page 111
    Boxed Processor Specifications Figure 8-9. 4-Pin Fan Cable Connector (For Active CEK Heat Sink) 111
  • Intel E5440 | Data Sheet - Page 112
    Boxed Processor Specifications Figure 8-10. 4-Pin Base Board Fan Header (For Active CEK Heat Sink) 112
  • Intel E5440 | Data Sheet - Page 113
    that are in proper alignment with each other to support the boxed processor. Refer to the Server System Infrastructure Specification (SSI-EEB 3.6, TEB 2.1 fan heat sink solution is connected to an older 3-pin baseboard CPU fan header it will default back to a thermistor controlled mode, allowing
  • Intel E5440 | Data Sheet - Page 114
    or on the baseboard itself. The baseboard fan power header should be positioned within 177.8 mm [7 in.] from the center of the processor socket. Table 8-1. PWM Fan Frequency Specifications for 4-Pin Active CEK Thermal Solution Description PWM Control Frequency Range Min Frequency 21,000 Nominal
  • Intel E5440 | Data Sheet - Page 115
    problems related to shock and vibration. The board must not bend beyond specification in order to avoid damage. The boxed processor contains the components necessary to solve both issues. The boxed processor will include the following items: • Quad-Core Intel® Xeon® Processor manual • Intel Inside
  • Intel E5440 | Data Sheet - Page 116
    Boxed Processor Specifications § 116
  • Intel E5440 | Data Sheet - Page 117
    following information is general in nature. Specific information must be obtained from the logic analyzer vendor. Due to the complexity of Quad-Core Intel® Xeon® Processor 5400 Series-based multiprocessor systems, the LAI is critical in providing the ability to probe and capture FSB signals. There
  • Intel E5440 | Data Sheet - Page 118
    installed between the processor socket and the processor. The LAI plugs into the socket, while the processor plugs into a socket on the LAI of the LAI. Electrical Considerations The LAI will also affect the electrical performance of the FSB, therefore it is critical to obtain electrical load models
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318589-005
Quad-Core Intel® Xeon® Processor
5400 Series
Datasheet
August 2008