Intel E8200 Data Sheet

Intel E8200 - Cpu Core 2 Duo 2.66Ghz Fsb1333Mhz 6M Lga775 Tray Manual

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  • Intel E8200 | Data Sheet - Page 1
    Intel® Core™2 Duo Processor E8000Δ and E7000Δ Series Datasheet June 2009 Document Number: 318732-006
  • Intel E8200 | Data Sheet - Page 2
    changes to them. The Intel Core™2 Duo processor E8000 and E7000 series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within
  • Intel E8200 | Data Sheet - Page 3
    1.1 Terminology ...10 1.1.1 Processor Terminology Definitions 10 1.2 References ...12 2 Electrical Specifications 13 2.1 Power and Ground Lands 13 2.2 Decoupling Guidelines 13 2.2.1 VCC Decoupling 13 2.2.2 VTT Decoupling 13 2.2.3 FSB Decoupling 14 2.3 Voltage Identification 14 2.4 Reserved
  • Intel E8200 | Data Sheet - Page 4
    State 91 6.2.8 Enhanced Intel SpeedStep® Technology 92 6.3 Processor Power Status Indicator (PSI) Signal 92 7 Boxed Processor Specifications 93 7.1 Introduction ...93 7.2 Mechanical Specifications 94 7.2.1 Boxed Processor Cooling Solution Dimensions 94 7.2.2 Boxed Processor Fan Heatsink Weight
  • Intel E8200 | Data Sheet - Page 5
    Thermal Profile 79 15 Intel® Core™2 Duo Processor E7000 Series Thermal Profile 80 16 Case Temperature (TC) Measurement Location 81 17 Thermal Monitor 2 Frequency and Voltage Ordering 83 18 Conceptual Fan Control Diagram on PECI-Based Platforms 85 19 Processor Low Power State Machine 88 20
  • Intel E8200 | Data Sheet - Page 6
    Land Assignment 56 26 Signal Description...66 27 Processor Thermal Specifications 78 28 Intel® Core™2 Duo Processor E8000 Series Thermal Profile 79 29 Intel® Core™2 Duo Processor E7000 Series Thermal Profile 80 30 GetTemp0() Error Codes 86 31 Power-On Configuration Option Signals 87 32
  • Intel E8200 | Data Sheet - Page 7
    at 3.06 GHz, 2.93 GHz, 2.80 GHz, 2.66 GHz, and 2.53 GHz for the Intel Core™2 Duo processor E7000 series • Enhanced Intel Speedstep® Technology • Supports Intel® 64Φ architecture • Supports Intel® Virtualization Technology (Intel® VT) (Intel Core™2 Duo processors E8600, E8500, E8400, E8300, E8200 and
  • Intel E8200 | Data Sheet - Page 8
    • Added the PSI# signal • Added Intel® Core™2 Duo processor E8600 and E7300 • Updated FSB termination voltage in Table 2-3. • Added Intel® Core™2 Duo processor E7400 • Added Intel® Core™2 Duo processor E7500 • Added Intel® Core™2 Duo processor E7600 § § Revision Date January 2008 April 2008 August
  • Intel E8200 | Data Sheet - Page 9
    Bit, Intel 64 architecture, and Enhanced Intel SpeedStep® Technology. The Intel Core™2 Duo processor E8600, E8500, E8400, E8300, and E8200 support Intel Trusted Execution Technology (Intel TXT) and Intel Virtualization Technology (Intel VT). The Intel Core™2 Duo processor E7600 supports Intel
  • Intel E8200 | Data Sheet - Page 10
    ® Core™2 Duo processor E8000 series and Intel® Core™2 Duo processor E7000 series. • Voltage Regulator Design Guide - For this document "Voltage Regulator Design Guide" may be used in place of: - Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket
  • Intel E8200 | Data Sheet - Page 11
    trade-offs to be made between performance and power consumptions, based on processor utilization. This may lower average power consumption (in conjunction with OS support). • Intel® Virtualization Technology (Intel® VT) - A set of hardware enhancements to Intel server and client platforms that can
  • Intel E8200 | Data Sheet - Page 12
    ® Core™2 Duo Processor E8000 and E7000 Series and Intel® Pentium Dual-Core Processor E6000 and E5000 Series Thermal and Mechanical Design Guidelines Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket LGA775 Socket Mechanical Design Guide Intel® 64
  • Intel E8200 | Data Sheet - Page 13
    content generated by the front side bus and processor activity. Consult the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for further information. Contact your Intel field representative for additional information. VTT Decoupling Decoupling
  • Intel E8200 | Data Sheet - Page 14
    that two devices at the same core speed may have different default VID settings. This is reflected by the VID Range values provided in Table 4. Refer to the Intel® Core™2 Duo Processor E8000 and E7000 Series Specification Update for further details on specific valid core frequency and VID values of
  • Intel E8200 | Data Sheet - Page 15
    Electrical Specifications Table 2. Voltage Identification Definition VID VID VID VID VID VID VID VID 76543210 Voltage 00000000 OFF 00000010 1.6 0 0 0 0 0 1 0 0 1.5875 0 0 0 0 0 1 1 0 1.575 0 0 0 0 1 0 0 0 1.5625 00001010 1.55 0 0 0 0 1 1 0 0 1.5375 0 0 0 0 1 1 1 0 1.525 0 0 0 1 0 0 0
  • Intel E8200 | Data Sheet - Page 16
    for designs supporting boundary scan for proper Boundary Scan testing of the processor in use requires more power than the platform voltage regulator (VR) is capable of supplying. For example, a 130 W TDP processor installed in a board with a 65 W or 95 W TDP capable VR may draw too much power
  • Intel E8200 | Data Sheet - Page 17
    clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long-term reliability of the device. For functional operation, refer to the processor case temperature specifications. 4. This rating applies to the processor and does not include any tray or
  • Intel E8200 | Data Sheet - Page 18
    6, Figure 2 V 3, 4, 5 VCC_BOOT VCCPLL ICC Default VCC voltage for initial power up PLL VCC Product Number (6 MB Cache): ICC for 775_VR_CONFIG_06: E8600 3.33 GHz E8500 3.16 GHz E8400 3 GHz E8300 2.83 GHz E8200 2.66 GHz E8190 2.66 GHz Processor Number (3 MB Cache): E7600 E7500 E7400
  • Intel E8200 | Data Sheet - Page 19
    line. Refer to the Voltage Regulator Design Guide to determine the total ITT drawn by the system. This parameter is based on design characterization and is not tested. 10. Adherence to the voltage specifications for the processor are required to ensure reliable processor operation. Datasheet 19
  • Intel E8200 | Data Sheet - Page 20
    Electrical Specifications Table 5. Intel® Core™2 Duo Processor E8000 Series VCC Static and Transient Tolerance ICC (A) Voltage Deviation from VID Setting (V)1, 2, 3, 4 Maximum Voltage 1.40 mΩ Typical Voltage 1.48 mΩ Minimum Voltage 1.55 mΩ 0 0.000 5 -0.007 10 -0.014 15 -0.021 20 -0.
  • Intel E8200 | Data Sheet - Page 21
    Electrical Specifications Figure 1. Intel® Core™2 Duo Processor E8000 Series VCC Static and Transient Tolerance Vcc [V] 0 VID - 0.000 VID - 0.013 VID - 0.025 VID - 0.038 VID - 0.050 VID - 0.063 VID - 0.075 VID - 0.088 VID - 0.
  • Intel E8200 | Data Sheet - Page 22
    Electrical Specifications Table 6. Intel® Core™2 Duo Processor E7000 Series VCC Static and Transient Tolerance ICC (A) Voltage Deviation from VID Setting (V)1, 2, 3, 4 Maximum Voltage 1.65 mΩ Typical Voltage 1.73 mΩ Minimum Voltage 1.80 mΩ 0 0.000 -0.019 -0.038 5 -0.008 -0.028 -0.047
  • Intel E8200 | Data Sheet - Page 23
    Electrical Specifications Figure 2. 2.6.3 Table 7. Intel® Core™2 Duo Processor E7000 Series VCC Static and Transient Tolerance Vcc [V] 0 VID - 0.000 VID - 0.013 VID - 0.025 VID - 0.038 VID - 0.050 VID - 0.063 VID - 0.075 VID - 0.088 VID - 0.
  • Intel E8200 | Data Sheet - Page 24
    limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit. Signaling Specifications Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings
  • Intel E8200 | Data Sheet - Page 25
    Specifications comes the need to specify two sets of timing parameters. One set is for common clock signals which Drain Input/ Output FSB Clock Power/Other Synchronous to BCLK[1:0] Clock processor systems where no debug port is implemented on the system board, these signals are used to support
  • Intel E8200 | Data Sheet - Page 26
    Specifications . Table 9. Table 10. 3. The value of these signals during the active-to-inactive edge of RESET# defines the processor their high-voltage level. Signal Reference Voltages GTLREF BPM[5:0]#, processor to recognize the proper signal state. See Section 2.7.3 for the DC specifications
  • Intel E8200 | Data Sheet - Page 27
    section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated. GTL+ Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 VIL VIH VOH IOL ILI Input Low Voltage -0.10 GTLREF - 0.10
  • Intel E8200 | Data Sheet - Page 28
    VTT * 0.10 / 27 A 6, 7 N/A ± 100 µA 8 N/A ± 100 µA 9 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. All outputs are open drain. 3. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical
  • Intel E8200 | Data Sheet - Page 29
    14. . Platform Environment Control Interface (PECI) DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors, chipsets, and external thermal monitoring devices. The processor contains Digital Thermal Sensors (DTS) distributed
  • Intel E8200 | Data Sheet - Page 30
    NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. GTLREF is to be generated from VTT by a voltage divider of 1% resistors. If an Adjustable GTLREF circuit is used on the board (for Quad-Core processors compatibility), the two GTLREF lands
  • Intel E8200 | Data Sheet - Page 31
    93 GHz 3.06 GHz 3.20 GHz 3.33 GHz 3.46 GHz 3.60GHz 3.73 GHz 4 GHz Core Frequency (333 MHz BCLK/ 1333 MHz FSB) 2 GHz 2.33 GHz 2.50 GHz 2.66 GHz 2.83 GHz 3 GHz 3.16 GHz 3.33 GHz 3.50 GHz 3.66 GHz 3.83 GHz 4 GHz 4.16 GHz 4.33 GHz 4.50 GHz 4.66 GHz 5 GHz Notes1, 2 - NOTES: 1. Individual processors
  • Intel E8200 | Data Sheet - Page 32
    by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency. The Intel® Core™2 Duo processor E7000 series noted, all specifications in this table apply to all processor frequencies. 2. Crossing voltage is defined as the instantaneous voltage value when the
  • Intel E8200 | Data Sheet - Page 33
    4. Slew rate is measured through the VSWING voltage range centered about differential zero. Measurement taken from 4 3 54 - 5 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor core frequencies based on a 266 MHz BCLK[1:0]. 2. The period specified
  • Intel E8200 | Data Sheet - Page 34
    Electrical Specifications Figure 4. 5. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75 mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage
  • Intel E8200 | Data Sheet - Page 35
    Package Mechanical Specifications 3 Package Mechanical Specifications Figure 6. The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA8) package that interfaces with the motherboard using an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An
  • Intel E8200 | Data Sheet - Page 36
    Figure 7. Processor Package Drawing Sheet 1 of 3 Package Mechanical Specifications 36 Datasheet
  • Intel E8200 | Data Sheet - Page 37
    Package Mechanical Specifications Figure 8. Processor Package Drawing Sheet 2 of 3 Datasheet 37
  • Intel E8200 | Data Sheet - Page 38
    Figure 9. Processor Package Drawing Sheet 3 of 3 Package Mechanical Specifications 38 Datasheet
  • Intel E8200 | Data Sheet - Page 39
    clip must also provide the minimum specified load on the processor package. 3. These specifications are based on limited testing for design characterization. Loading limits are for the package only and do not include the limits of the processor socket. 4. Dynamic loading is defined as an 11 ms
  • Intel E8200 | Data Sheet - Page 40
    Fiber Reinforced Resin Gold Plated Copper 3.8 Processor Markings Figure 10. Figure 10 shows the top-side markings on the processor. This diagram is to aid in the identification of the processor. Processor Top-Side Markings Example INTEL M ©'06 E8500 Intel® Core®2 Duo SLxxx [COO] 3.16GHZ/6M/1333
  • Intel E8200 | Data Sheet - Page 41
    Package Mechanical Specifications 3.9 Processor Land Coordinates . Figure 11. Figure 11 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. Processor Land Coordinates and Quadrants, Top View V CC / V SS 30
  • Intel E8200 | Data Sheet - Page 42
    Package Mechanical Specifications 42 Datasheet
  • Intel E8200 | Data Sheet - Page 43
    and Signal Descriptions 4 4.1 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 12 and Figure 13. These
  • Intel E8200 | Data Sheet - Page 44
    Land Listing and Signal Descriptions Figure 12. land-out Diagram (Top View - Left Side) 30 29 28 AN VCC VCC VSS 27 VSS 26 VCC 25 VCC 24 VSS 23 VSS 22 VCC 21 VCC 20 VSS 19 VCC 18 VCC 17 VSS 16 VSS 15 VCC AM VCC VCC VSS AL VCC VCC VSS AK VSS VSS VSS AJ VSS VSS VSS AH VCC VCC
  • Intel E8200 | Data Sheet - Page 45
    Land Listing and Signal Descriptions Figure 13. land-out Diagram (Top View - Right Side) 14 VCC VCC VCC VCC VCC VCC VCC VCC VCC 13 VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VSS 12 VCC VCC VCC VCC VCC VCC VCC VCC VCC 11 VCC VCC VCC VCC VCC VCC VCC VCC VCC 10 VSS VSS VSS VSS VSS VSS VSS
  • Intel E8200 | Data Sheet - Page 46
    Clock Input/Output G29 Asynch CMOS Output H30 Asynch CMOS Output G30 Asynch CMOS Output A13 Power/Other Input T1 Power/Other Input G2 Power/Other Input R1 Power/Other Input B13 Power/Other Input B4 Source Synch Input/Output C5 Source Synch Input/Output A4 Source Synch Input/Output
  • Intel E8200 | Data Sheet - Page 47
    /Output Y1 Power/Other J2 F2 AK6 E24 H29 AE3 E5 F6 J3 A24 AK1 AL1 E29 G1 U1 U2 U3 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Datasheet
  • Intel E8200 | Data Sheet - Page 48
    Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction FC31 FC32 FC33 FC34 FC35 J16 H15 H16 J17 H4 Power/Other Power/Other Power/Other Power/Other Power/Other FC36 FC37 FC38 FC39 FC40 FC41 FERR#/PBE# GTLREF0 GTLREF1 HIT# HITM# IERR# IGNNE# INIT# ITP_CLK0 ITP_CLK1 LINT0
  • Intel E8200 | Data Sheet - Page 49
    VCC VCC AF22 Power/Other AF8 Power/Other AF9 Power/Other AG11 Power/Other AG12 Power/Other AG14 Power/Other AG15 Power/Other AG18 Power/Other AG19 Power/Other AG21 Power/Other AG22 Power/Other AG25 Power/Other AG26 Power/Other AG27 Power/Other AG28 Power/Other AG29 Power/Other AG30 Power/Other AG8
  • Intel E8200 | Data Sheet - Page 50
    Power/Other AN19 Power/Other AN21 Power/Other AN22 Power/Other AN25 Power/Other AN26 Power/Other AN29 Power/Other AN30 Power/Other AN8 Power/Other AN9 Power/Other J10 Power/Other J11 Power/Other J12 Power/Other J13 Power/Other J14 Power/Other J15 Power/Other J18 Power/Other J19 Power/Other J20 Power
  • Intel E8200 | Data Sheet - Page 51
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel E8200 | Data Sheet - Page 52
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel E8200 | Data Sheet - Page 53
    AG13 Power/Other AG16 Power/Other AG17 Power/Other AG20 Power/Other AG23 Power/Other AG24 Power/Other AG7 Power/Other AH1 Power/Other AH10 Power/Other AH13 Power/Other AH16 Power/Other AH17 Power/Other AH20 Power/Other AH23 Power/Other AH24 Power/Other AH3 Power/Other AH6 Power/Other AH7 Power/Other
  • Intel E8200 | Data Sheet - Page 54
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel E8200 | Data Sheet - Page 55
    V7 W4 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel E8200 | Data Sheet - Page 56
    /Other A22 D62# Source Synch Input/Output A23 VCCA Power/Other A24 FC23 Power/Other A25 VTT Power/Other A26 VTT Power/Other A27 VTT Power/Other A28 VTT Power/Other A29 VTT Power/Other A30 VTT Power/Other B1 VSS Power/Other B2 DBSY# Common Clock Input/Output B3 RS0
  • Intel E8200 | Data Sheet - Page 57
    /Output D58# Source Synch Input/Output VSS Power/Other VCCIOPLL Power/Other VSS Power/Other VTT Power/Other VTT Power/Other VTT Power/Other VTT Power/Other VTT Power/Other VTT Power/Other RESERVED ADS# Common Clock Input/Output VSS Power/Other HIT# Common Clock Input/Output
  • Intel E8200 | Data Sheet - Page 58
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel E8200 | Data Sheet - Page 59
    /Output A03# Source Synch Input/Output VSS Power/Other VSS Power/Other VCC Power/Other VSS Power/Other VSS Power/Other VSS Power/Other VSS Power/Other VSS Power/Other VSS Power/Other VSS Power/Other VSS Power/Other VSS Power/Other THERMTRIP # Asynch CMOS Output STPCLK
  • Intel E8200 | Data Sheet - Page 60
    /Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output
  • Intel E8200 | Data Sheet - Page 61
    Output W7 VSS Power/Other W8 VCC Power/Other W23 VCC Power/Other W24 VCC Power/Other W25 VCC Power/Other W26 VCC Power/Other W27 VCC Power/Other W28 VCC Power/Other W29 VCC Power/Other W30 VCC Power/Other Y1 FC0/ BOOTSELECT Power/Other Y2 VSS Power/Other Table 25
  • Intel E8200 | Data Sheet - Page 62
    Output VCC Power/Other VSS Power/Other VCC Power/Other VCC Power/Other VSS Power/Other VCC Power/Other VCC Power/Other VSS Power/Other VSS Power/Other VCC Power/Other VCC Power/Other VSS Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VSS Power/Other VSS
  • Intel E8200 | Data Sheet - Page 63
    Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Datasheet 63
  • Intel E8200 | Data Sheet - Page 64
    Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS Input/Output Power/Other Asynch CMOS Output Asynch CMOS Output Asynch CMOS Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other 64
  • Intel E8200 | Data Sheet - Page 65
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel E8200 | Data Sheet - Page 66
    bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-MB boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the
  • Intel E8200 | Data Sheet - Page 67
    agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by de-asserting BPRI#. Input/ Output BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this signal is sampled to determine the agent ID
  • Intel E8200 | Data Sheet - Page 68
    processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad data bus is inverted. If more than half the data bits, within a 16-bit group, would have been asserted electrically low, the bus
  • Intel E8200 | Data Sheet - Page 69
    low power state, requires chipset support and may not be available on all platforms. NOTE: Some processors may not have the Deep Sleep State enabled, refer to the Specification Update for specific processor and stepping guidance. Input/ Output DRDY# (Data Ready) is asserted by the data driver on
  • Intel E8200 | Data Sheet - Page 70
    event functionality, including the identification of support of the feature and enable/disable information, refer to volume 3 of the Intel Architecture Software Developer's Manual and the Intel Processor Identification and the CPUID Instruction application note. Input GTLREF[1:0] determine the
  • Intel E8200 | Data Sheet - Page 71
    these signals are connected on the package to VSS. As an alternative to MSID, Intel has implemented the Power Segment Identifier (PSID) to report the maximum Thermal Design Power of the processor. Refer to Section 2.5 for additional information regarding PSID. Input/ PECI is a proprietary one-wire
  • Intel E8200 | Data Sheet - Page 72
    Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications lands of all processor FSB agents. SKTOCC# (Socket Occupied) will be pulled to ground by the Output processor. System board
  • Intel E8200 | Data Sheet - Page 73
    input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. Output TDO provides the serial output needed for JTAG specification support. Input The TESTHI[12,10:0] lands must be connected to the processor's appropriate power source (refer to
  • Intel E8200 | Data Sheet - Page 74
    de-assert THERMTRIP#, if the processor's junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within 10 μs of the assertion of PWRGOOD (provided VTT and VCC are valid). Input TMS (Test Mode Select) is a JTAG specification support signal used by debug tools
  • Intel E8200 | Data Sheet - Page 75
    VTT_SEL Output The VID (Voltage ID) signals are used to support automatic selection of power supply voltages (VCC). Refer to the Voltage Regulator Design Guide for more information. The voltage supply for these signals must be valid before the VR can supply VCC to the processor. Conversely, the VR
  • Intel E8200 | Data Sheet - Page 76
    Land Listing and Signal Descriptions 76 Datasheet
  • Intel E8200 | Data Sheet - Page 77
    . To determine a processor's case temperature specification based on the thermal profile, it is necessary to accurately measure processor power dissipation. Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions. Refer to
  • Intel E8200 | Data Sheet - Page 78
    processor to remain within specification. Table 27. Processor Thermal Specifications Processor Number Core Frequency (GHz) Thermal Design Power (W)3,4 Extended HALT Power (W)1 E8600 3.33 65.0 8 E8500 3.16 65.0 8 E8400 3 65.0 8 E8300 2.83 65.0 8 E8200 2.66 65.0 8 E8190 2.66
  • Intel E8200 | Data Sheet - Page 79
    65 20 53.5 44 63.6 22 54.3 46 64.4 Maximum Tc (°C) 65.3 66.1 66.9 67.8 68.6 69.5 70.3 71.1 72.0 72.4 Figure 14. Intel® Core™2 Duo Processor E8000 Series Thermal Profile Tcase (C) 72.0 68.0 64.0 60.0 56.0 52.0 48.0 44.0 0 y = 0.42x + 45.1 10 20 30 40 50 60 Power (W) Datasheet 79
  • Intel E8200 | Data Sheet - Page 80
    57.5 58.4 59.3 60.2 61.1 62.0 62.9 63.8 64.7 65.6 Power 48 50 52 54 56 58 60 62 64 65 Maximum Tc (°C) 66.5 67.4 68.3 69.2 70.1 71.0 71.9 72.8 73.7 74.1 Figure 15. Intel® Core™2 Duo Processor E7000 Series Thermal Profile Tcase (C) 72.0 68.0 64.0 60.0 56.0 52.0 48.0 44.0 0 y = 0.45x + 44.9 10
  • Intel E8200 | Data Sheet - Page 81
    reaches its maximum operating temperature. The TCC reduces processor power consumption by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor feature must be enabled for the processor to be operating within specifications. The temperature at which Thermal
  • Intel E8200 | Data Sheet - Page 82
    continues to execute instructions during the voltage transition. Operation at the lower voltage reduces the power consumption of the processor. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum
  • Intel E8200 | Data Sheet - Page 83
    to limit the processor temperature. If bit 4 of the ACPI P_CNT Control Register (located in the processor IA32_THERM_CONTROL MSR) is written to a '1', the processor will immediately reduce its power consumption using modulation (starting and stopping) of the internal core clock, independent of
  • Intel E8200 | Data Sheet - Page 84
    must be designed to ensure the processor remains within specification. If the processor enters one of the above low-power states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the low-power state and the processor DTS temperature drops below the thermal trip
  • Intel E8200 | Data Sheet - Page 85
    control solutions based on PECI utilize a TCONTROL value stored in the processor IA32_TEMPERATURE_TARGET MSR. The TCONTROL MSR uses the same offset temperature format as PECI though it contains no sign bit. Thermal management devices should infer the TCONTROL value as negative. Thermal management
  • Intel E8200 | Data Sheet - Page 86
    Support PECI command support is covered in detail in the Platform Environment Control Interface Specification. Refer to this document for details on supported a default power-on condition that ensures proper processor operation during the client processor device if valid temperature readings have not
  • Intel E8200 | Data Sheet - Page 87
    configuring the EXT_CONFIG Model Specific Register (MSR). This MSR will allow for the disabling of a single core per die within the processor package. 6.2 Clock Control and Low Power States The processor allows the use of AutoHALT and Stop-Grant states to reduce power consumption by stopping the
  • Intel E8200 | Data Sheet - Page 88
    HALT is a low power state entered when all the processor cores have executed the HALT or MWAIT instructions. When one of the processor cores executes the HALT instruction, that processor core is halted, however, the other processor continues normal operation. The halted core will transition to the
  • Intel E8200 | Data Sheet - Page 89
    within its specification. The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended HALT state. Note that the processor FSB frequency is not altered; only the internal core frequency is changed. When entering the low power state, the
  • Intel E8200 | Data Sheet - Page 90
    serviced the processor will return to the Extended HALT state or Extended Stop Grant state. Sleep State The Sleep state is a low power state in which the processor the processor is not in these states is out of specification and may result in unapproved operation. In the Sleep state, the processor is
  • Intel E8200 | Data Sheet - Page 91
    processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor Deep Sleep state for additional platform level power savings. BCLK stop/restart timings on similar to the Deep Sleep state but the core voltage is reduced to a lower level. The
  • Intel E8200 | Data Sheet - Page 92
    power savings. To support this technology, the system must support dynamic VID transitions. Switching between voltage/frequency states is software controlled. Enhanced Intel SpeedStep Technology is a technology that creates processor performance states (P states). P states are power consumption
  • Intel E8200 | Data Sheet - Page 93
    in millimeters and inches [in brackets]. Figure 20 shows a mechanical representation of a boxed processor. Note: Figure 20. Drawings in this section reflect only the specifications on the Intel boxed processor product. These dimensions should not be used as a generic keep-out zone for all cooling
  • Intel E8200 | Data Sheet - Page 94
    Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 20 shows a mechanical representation of the boxed processor. Figure 21. Clearance is required around the fan
  • Intel E8200 | Data Sheet - Page 95
    will be shipped with the boxed processor to draw power from a power header on the baseboard. The power cable connector and pinout are shown in Figure 24. Baseboards must provide a matched power header to support the boxed processor. Table 32 contains specifications for the input and output signals
  • Intel E8200 | Data Sheet - Page 96
    Processor Specifications Figure 24. The boxed processor's fanheat sink requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control. The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power
  • Intel E8200 | Data Sheet - Page 97
    Boxed Processor Specifications Figure 25. Baseboard Power Header Placement Relative to Processor Socket R110 [4.33] B C 7.4 7.4.1 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. Boxed Processor Cooling Requirements
  • Intel E8200 | Data Sheet - Page 98
    Boxed Processor Specifications Figure 26. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) Figure 27. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view) 98 Datasheet
  • Intel E8200 | Data Sheet - Page 99
    speed fan for the boxed processor. Refer to Table 32 for the specific requirements. Boxed Processor Fan Heatsink Set Points Increasing Fan Speed & Noise Higher Set Point Highest Noise Level Lower Set Point Lowest Noise Level X Y Z Internal Chassis Temperature (Degrees C) Datasheet 99
  • Intel E8200 | Data Sheet - Page 100
    Boxed Processor Specifications Table 33. Fan Heatsink Power and Signal Specifications Boxed Processor Fan Heatsink Set Point (°C) Boxed Processor Fan Speed Notes X ≤ 30 When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. 1
  • Intel E8200 | Data Sheet - Page 101
    Specific information must be obtained from the logic analyzer vendor. Due to the complexity of Intel Core™2 Duo processor E8000 and E7000 series systems, the LAI is critical in providing the ability to probe and capture FSB signals. There are two sets affect the electrical performance of the FSB;
  • Intel E8200 | Data Sheet - Page 102
    Debug Tools Specifications 102 Datasheet
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Document Number: 318732-006
Intel
®
Core™2 Duo Processor E8000
Δ
and E7000
Δ
Series
Datasheet
June 2009