Intel SL3VS Specification Update

Intel SL3VS - Celeron 633 MHz Processor Manual

Get Intel SL3VS - Celeron 633 MHz Processor PDF manuals and user guides View all Intel SL3VS manuals
Add to My Manuals
Save this manual to your list of manuals

Intel SL3VS manual content summary:

  • Intel SL3VS | Specification Update - Page 1
    Specification Update Release Date: August 2007 Document Number: 243748-051 The Intel® Celeron® processor may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are documented in
  • Intel SL3VS | Specification Update - Page 2
    distributor to obtain the latest specifications and before placing your product order. Intel, Pentium, Celeron, Intel Xeon and the Intel logo are trademarks or registered trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries*Other names
  • Intel SL3VS | Specification Update - Page 3
    for the Intel® Celeron® Processor 1 GENERAL INFORMATION...1 Intel® Celeron® Processor and Boxed Intel® Celeron® Processor Markings (S.E.P. Package 1 Intel® Celeron® Processor and Boxed Intel® Celeron® Processor Markings (PPGA Package 2 Intel® Celeron® Processor and Boxed Intel® Celeron® Processor
  • Intel SL3VS | Specification Update - Page 4
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE REVISION HISTORY Date of Revision 012 -013 -014 -015 -016 Description This document is the first Specification Update for the Intel® Celeronc processor. Added Errata 24 through 28. Updated S-spec Table. Updated Summary Table of Changes. Updated
  • Intel SL3VS | Specification Update - Page 5
    Erratum C74. Added Documentation Changes C9 and C10 Updated the Intel® Celeron® Processor Identification Information table Added Errata C75 and C76. Updated Specification Update product key to include the Intel® Pentium® 4 processor, Updated Erratum C2. Added Documentation changes C11, C12, C13, C14
  • Intel SL3VS | Specification Update - Page 6
    -040 -041 -042 -043 -044 Description Updated the Intel® Celeron® Processor Identification Information table. Updated the Summary of Errata table. Added numbers of the Software Developers Manual. Updated Processor Identification Table. Added Erratum C110. Updated Summary Table of Changes. iv
  • Intel SL3VS | Specification Update - Page 7
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE REVISION HISTORY Date of Revision Version August 2007 -051 Description Updated Summary Table of Changes. Added Erratum C111. v
  • Intel SL3VS | Specification Update - Page 8
    Pentium® II Processor Developer's Manual (Order Number 243502) • P6 Family of Processors Hardware Developer's Manual (Order Number 244001) • Intel® Celeron® Processor Datasheet (Document Number 243658) • Intel® 64 and Intel core speed, L2 cache size, package type, etc. as described in the processor
  • Intel SL3VS | Specification Update - Page 9
    Specification Update for the Intel® Celeron® Processor GENERAL INFORMATION Intel® Celeron® Processor and Boxed Intel® Celeron® Processor Markings (S.E.P. Package) Static White Silkscreen marks celeron ™ ® Dynamic laser mark area NOTES: • SYYYY = S-spec Number. • FFFFFFFF = FPO # (Test Lot
  • Intel SL3VS | Specification Update - Page 10
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Intel® Celeron® Processor and Boxed Intel® Celeron® Processor Markings (PPGA Package) Top Bottom intel ® celeronTM AAAAAAAZZZ LLL SYYYY i Country of Origin FFFFFFFF-XXXX M C '98 NOTES: ƒ AAAAAAA = Product Code ƒ ZZZ = Processor Speed (MHz) ƒ LLL =
  • Intel SL3VS | Specification Update - Page 11
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Intel® Celeron® Processor and Boxed Intel® Celeron® Processor Markings (FC-PGA/FC-PGA2 Package) FC-PGA 370 Pin Package GRP1LN1: INTEL (m)(c) '01_-_{COO} GRP1LN2: {Core Freq}/{Cache}/{Bus Freq}/{Voltage} GRP2LN1: {FPO}-{S/N} GRP2LN2: CELERON {S-Spec} FC
  • Intel SL3VS | Specification Update - Page 12
    0110 0110 0110 1000 10114 00h = Not Supported 01h = "Intel® Celeron® Processor" 03h = "Intel® Celeron® Processor" NOTES: 1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register
  • Intel SL3VS | Specification Update - Page 13
    SL39Z SL37V SL3BC SL35Q SL35Q SL36A SL35R SL36B SL36C SL35S INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Intel® Celeron® Processor Identification Information Core Stepping A0 L2 Cache Size (Kbytes) 0 CPUID 0650h Speed (MHz) Core/Bus 266/66 Package and Revision SEPP Rev. 1 A0 0 0650h
  • Intel SL3VS | Specification Update - Page 14
    SL46S SL3W6 SL46T SL3W7 SL4PC SL4NW SL5L5 SL46U SL3W8 SL4PB SL4NX SL3VS SL3W9 SL4PA SL4NY SL48E SL4AB SL4P9 SL4NZ Intel® Celeron® Processor Identification Information Core Stepping B0 L2 Cache Size (Kbytes) 128 CPUID 0665h Speed (MHz) Core/Bus 400/66 Package and Revision PPGA B0 128 0665h
  • Intel SL3VS | Specification Update - Page 15
    SL5GA SL5GB SL54Q SL5EC SL5LX SL5WA SL5MQ SL5WY SL633 SL5UZ SL5V2 INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Intel® Celeron® Processor Identification Information Core Stepping B0 L2 Cache Size (Kbytes) 128 CPUID 0683h Speed (MHz) Core/Bus 700/66 Package and Revision FC-PGA B0 128 0683h
  • Intel SL3VS | Specification Update - Page 16
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE S-Spec SL634 Intel® Celeron® Processor Identification Information Core Stepping D0 L2 Cache Size (Kbytes) 128 CPUID 068Ah Speed (MHz) Core/Bus 950/100 Package and Revision FC-PGA2 Notes 2,8,14 8
  • Intel SL3VS | Specification Update - Page 17
    SL5Y5 SL656 SL68P SL6C8 SL6JS SL5VR SL5ZJ SL6C7 SL6JT SL64V SL68G INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Intel® Celeron® Processor Identification Information Core Stepping D0 L2 Cache Size (Kbytes) 128 CPUID 068Ah Speed (MHz) Core/Bus 1 GHz/100 Package and Revision FC-PGA D0 128
  • Intel SL3VS | Specification Update - Page 18
    SPECIFICATION UPDATE S-Spec SL6C6 SL6JU SL6C5 SL6JV Intel® Celeron® Processor Identification Information Core Stepping B1 B1 B1 B1 L2 Cache Size (Kbytes) 256 256 256 256 CPUID 06B4h 06B4h 06B4h 06B4h Speed (MHz) Core/Bus 1.40 GHz/100 1.40 GHz/100 1.50 GHz/100 1.50 GHz/100 Package and
  • Intel SL3VS | Specification Update - Page 19
    with 1 MB L2 Cache K = Mobile Intel® Pentium® III processor L = Intel® Celeron® D processor M = Mobile Intel® Celeron® processor N = Intel® Pentium® 4 processor O = Intel® Xeon® processor MP P = Intel® Xeon® processor Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading Technology on 90
  • Intel SL3VS | Specification Update - Page 20
    AD = Intel® Celeron® D processor on 65 nm process AE = Intel® Core™ Duo Processor and Intel® Core™ Solo processor on 65 nm process AF = Dual-Core Intel® Xeon® processor LV AG = Dual-Core Intel® Xeon® Processor 5100 Series AH = Intel® Core™2 Duo/Solo Processor for Intel® Centrino® Duo Processor
  • Intel SL3VS | Specification Update - Page 21
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata NO. CPUID/Stepping Plans ERRATA traffic C18 X Fixed Snoop cycle generates spurious machine check exception C19 X X Fixed MOVD/MOVQ instruction writes to memory prematurely C20 X X X X X X X X X NoFix Memory type
  • Intel SL3VS | Specification Update - Page 22
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata NO. CPUID/ WRMSR to invalid MSR address may not cause GP fault C37 X X X X X X X NoFix SYSENTER/SYSEXIT instructions can implicitly load "null segment selector" to SS and CS registers C38 X X X X X X X NoFix
  • Intel SL3VS | Specification Update - Page 23
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata NO. CPUID/ access bit to be set C48 X X X X X X X X X NoFix Cross-modifying code operations on a jump instruction may cause a general protection fault C49 X X X X X X X Fixed Deadlock may occur due to illegal
  • Intel SL3VS | Specification Update - Page 24
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata NO. CPUID/Stepping Plans 650h 651h 660h 665h 683h 686h 68Ah 6B1h 6B4h A0 A1 A0 B0 B0 C0 D0 A1 B1 ERRATA C53 X X X X X NoFix FLUSH# servicing hang C66 X Fixed MASKMOVQ instruction interaction with string operation may
  • Intel SL3VS | Specification Update - Page 25
    INTEL® CELERON® PROCESSOR NoFix Processor may report invalid TSS fault instead of Double fault during mode C paging C75 X X Fixed APIC failure at CPU core/system instruction fetch unit (IFU) may fetch instructions based upon stale CR3 data after a write to CR3 Register C80 X NoFix Processor
  • Intel SL3VS | Specification Update - Page 26
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata NO. CPUID/ Violation May Occur on 4 Gigabyte Limit Check C90 X X X X X X X X X NoFix FST Instruction with Numeric and Null Segment Exceptions May Cause General Protection Faults to be Missed and FP Linear Address (FLA
  • Intel SL3VS | Specification Update - Page 27
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE NO. C93 C93 C94 C95 C96 C97 C98 C99 C100 650h A0 X X X X Under Certain Conditions LTR (Load Task Register) Instruction May Result in System Hang Under Certain Conditions LTR (Load Task Register) Instruction May Result in System Hang Loading from Memory
  • Intel SL3VS | Specification Update - Page 28
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE NO. C101 C102 C103 C104 C105 C106 for Non-Single-Step #DB Exception Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame Unaligned Accesses to Paging Structures May Cause the Processor to Hang INVLPG Operation for Large (2M/4M)
  • Intel SL3VS | Specification Update - Page 29
    UPDATE * Fix will be only on Celeron processors with CPUID=068xh. Summary of Documentation Changes CPUID/Stepping 650h 651h 660h 665h 683h 686h 68Ah 6B1h 6B4h NO. A0 A1 A0 B0 B0 C0 D0 A1 B1 Plans DOCUMENTATION CHANGES C1 X X X X X X X X X Doc SSE and SSE2 Instructions Opcodes C2
  • Intel SL3VS | Specification Update - Page 30
    ® CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Documentation Changes CPUID/Stepping 650h 651h 660h 665h 683h 686h 68Ah 6B1h 6B4h NO. A0 A1 A0 B0 B0 C0 D0 A1 B1 Plans DOCUMENTATION CHANGES C22 X X X X X X X X X Doc Cache Description C23 X X X X X X X X X Doc Instruction
  • Intel SL3VS | Specification Update - Page 31
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Specification Clarifications CPUID/Stepping 650h 651h 660h 665h 683h 686h 68Ah 6B1h 6B4h NO. A0 A1 A0 B0 B0 C0 D0
  • Intel SL3VS | Specification Update - Page 32
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Specification Changes CPUID/Stepping 650h 651h 660h X X X X X Doc RESET# pin definition C2 X X X Doc Tco max revision for 533A,566 & 600MHz C3 X X X X X Doc Processor thermal specification change and TDP redefined 24
  • Intel SL3VS | Specification Update - Page 33
    Problem: There exist some differences in the reporting of code and data breakpoint matches between that specified by previous Celeron processor specifications and the behavior of Celeron processor, as described below: Case 1: The first case is for a breakpoint set on a MOVSS or POPSS instruction
  • Intel SL3VS | Specification Update - Page 34
    on the instruction, the breakpoint is reported twice. Case 6: Unlike previous versions of Intel Architecture processors, Celeron processors will not will be serviced. Mixing data and code may exacerbate this problem by allowing disabled data breakpoint registers to break on an instruction fetch.
  • Intel SL3VS | Specification Update - Page 35
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C4. FP Inexact-Result Exception Flag May Not Be Set Problem: When the result of a floating-point operation is not exactly representable in the destination format (1/3 in binary form, for example), an inexact-result (precision) exception
  • Intel SL3VS | Specification Update - Page 36
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C6. I/O Restart in SMM May Fail After Simultaneous MCE Problem: If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed, and if the data for this instruction becomes corrupted, the Celeron processor will signal a machine check
  • Intel SL3VS | Specification Update - Page 37
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C9. LBER May Be Corrupted After Some Events Problem: The last branch record of this section. C10. BTMs May Be Corrupted During Simultaneous L1 Cache Line Replacement Problem: When Branch Trace Messages (BTMs) are enabled and such a message is generated,
  • Intel SL3VS | Specification Update - Page 38
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C11. Potential Early Deassertion of LOCK# During Split-Lock Cycles Problem: During a split-lock cycle there SMM state save map. Software then asserts A20M# and executes the RSM instruction. After exiting the SMM handler, the polarity of A20M# is inverted
  • Intel SL3VS | Specification Update - Page 39
    of this section. C13. Reporting of Floating-Point Exception May Be Delayed Problem: The Celeron processor normally reports a floating-point exception for an instruction when the next floating-point or Intel® MMX™ technology instruction is executed. The assertion of FERR# and/or the INT 16 interrupt
  • Intel SL3VS | Specification Update - Page 40
    . C16. THERMTRIP# May Not Be Asserted as Specified Problem: THERMTRIP# is a signal on the Celeron processor which is asserted when the core reaches a critical temperature during operation as detailed in the processor specification. The Celeron processor may not assert THERMTRIP# until a much higher
  • Intel SL3VS | Specification Update - Page 41
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C18. Snoop Cycle Generates Spurious Machine Check Exception Problem: The processor may incorrectly 0 case only occurs when the MOVD/MOVQ store is the first MMX instruction in an MMX technology routine and the previous floating-point routine did not
  • Intel SL3VS | Specification Update - Page 42
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE 3. The unmasked floating-point exception case only occurs if the store is the first MMX technology instruction of this section. C20. Memory Type Undefined for Nonmemory Operations Problem: The Memory Type field for nonmemory transactions such as I/O and
  • Intel SL3VS | Specification Update - Page 43
    in Section 8.2 of the Intel Architecture Software Developer's Manual, Volume 3: System Programming Guide (Order Number 243192). This recommendation states that if the FPU will be used, software-initialization code should execute an FINIT/FNINIT instruction following a hardware reset. This
  • Intel SL3VS | Specification Update - Page 44
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C23. MOVD Following Zeroing Instruction Can Cause Incorrect Result Problem: An incorrect result may be calculated after the following circumstances occur: 1. A register has been zeroed with either a SUB reg, reg instruction or an XOR reg, reg
  • Intel SL3VS | Specification Update - Page 45
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Workaround: There are two possible workarounds for this of a Load Operation Prior to Exception Handler Invocation Problem: This erratum can occur with any of the following situations: 1. If an instruction that performs a memory load causes a code
  • Intel SL3VS | Specification Update - Page 46
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C25. Read Portion of RMW Instruction May Execute Twice Problem: When the Celeron processor executes a read-modify-write (RMW) arithmetic instruction, with memory as the destination, it is possible for a page fault to occur during the execution of the
  • Intel SL3VS | Specification Update - Page 47
    Register Causes Debug Exception Problem: When in V86 mode, if a MOV instruction is executed on debug registers, a general-protection exception (#GP) should be generated, as documented in the Intel Architecture Software Developer's Manual, Volume 3: System Programming Guide, Section 15.2. However, in
  • Intel SL3VS | Specification Update - Page 48
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C30. Upper Four PAT Entries Not Usable With Mode B or Mode C Paging Problem: The Page Attribute Table (PAT) contains eight entries, which must all be initialized and considered when setting up memory types for the Celeron processor. However, in Mode B
  • Intel SL3VS | Specification Update - Page 49
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C32. Misprediction in Program Flow May Cause Unexpected Instruction Execution Problem: To C34. System Bus ECC Not Functional With 2:1 Ratio Problem: If a processor is underclocked at a core frequency to system bus frequency ratio of 2:1 and system
  • Intel SL3VS | Specification Update - Page 50
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Workaround: All bus agents that support system bus ECC must disable it GP Fault Problem: The RDMSR and WRMSR instructions allow reading or writing of MSRs (Model Specific Registers) based on the index number placed in ECX. The processor should reject
  • Intel SL3VS | Specification Update - Page 51
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C37. SYSENTER/SYSEXIT Instructions Can Implicitly Load "Null Segment Selector" to SS and CS Registers Problem: According to the processor specification, attempting to load a null segment selector into the CS and SS segment registers should generate a
  • Intel SL3VS | Specification Update - Page 52
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C39. Far Jump to New TSS With D-bit Cleared May Cause System Hang Problem: A task switch may be performed by executing a far jump through a task gate or to a new Task State Segment (TSS) directly. Normally, when such a jump to a
  • Intel SL3VS | Specification Update - Page 53
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C41. UC Write May Be Reordered Around a Cacheable Write Problem: After a write occurs to a Be Cleared After Debug Exception Problem: The Resume Flag (RF) is normally cleared by the processor after executing an instruction which causes a debug exception
  • Intel SL3VS | Specification Update - Page 54
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C43. Internal Cache Protocol Violation May Cause System Hang Problem: A Celeron processor-based system may hang due to an internal cache protocol violation. During multiple transactions targeted at the same cacheline, there exists a small window of time
  • Intel SL3VS | Specification Update - Page 55
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C45. Machine Check Exception May Occur Due to Improper Line Eviction in the IFU Problem: The Celeron processor processors, the risk is lower on Celeron processor-based systems as they do not have multi-processor support the WRMSR instruction will cause
  • Intel SL3VS | Specification Update - Page 56
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C47. Task Switch May Cause Wrong PTE and PDE Access Bit to be Set Problem: If an operating system executes a task algorithm as detailed in Volume 3 of the Intel Architecture Software Developer's Manual, section 7.1.3, in order to avoid this erratum
  • Intel SL3VS | Specification Update - Page 57
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C49. Deadlock May Occur Due To Illegal-Instruction/Page-Miss Combination Problem: Intel's 32-bit Instruction Set Architecture (ISA) utilizes most of the available op-code space; however some byte combinations remain undefined and are considered illegal
  • Intel SL3VS | Specification Update - Page 58
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C51. Floating-Point Exception Condition May be Deferred Problem: A floating-point instruction that causes a pending floating-point exception (ES=1) is normally signaled by the processor on the next waiting FP/MMX™ technology instruction. In the
  • Intel SL3VS | Specification Update - Page 59
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C53. FLUSH# Servicing Delayed While Waiting for STARTUP_IPI in 2-way MP Systems Problem: In a 2-way MP system, if an application processor is waiting for a startup inter-processor interrupt (STARTUP_IPI), then it will not service a FLUSH# pin assertion
  • Intel SL3VS | Specification Update - Page 60
    Multiprocessor TLB Shootdown Problem: This erratum may occur when the Celeron processor executes one of the following read-modifywrite arithmetic instructions and a the final arithmetic flag values although the instruction has not yet completed. Intel has not identified any operating systems that
  • Intel SL3VS | Specification Update - Page 61
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C57. Mixed Cacheability of Lock Variables Is Problematic in MP Systems Problem: This errata only affects multiprocessor systems where a lock variable address is marked cacheable in one processor and uncacheable in any others. The processors which have
  • Intel SL3VS | Specification Update - Page 62
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C59. Potential Loss of Data Coherency During MP Data Ownership Transfer Problem: In MP systems, processors may be sharing data in different cache lines, referenced as line A and line B in the discussion below. When this erratum occurs (with the
  • Intel SL3VS | Specification Update - Page 63
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C61. Memory Ordering Based Synchronization May Cause a Livelock Condition in MP Systems Problem: In an MP environment, the following sequence of code (or similar code) in two processors (P0 and P1) may cause them to each enter an infinite loop (
  • Intel SL3VS | Specification Update - Page 64
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C62. Processor May Assert DRDY# on a Write With No Data Problem: When a MASKMOVQ instruction is misaligned across a chunk boundary in a way that one chunk has a mask of all 0's, the processor will initiate two partial write transactions with one having
  • Intel SL3VS | Specification Update - Page 65
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Status: For the steppings affected, see the Summary of Changes at the beginning of this section. C66. MASKMOVQ Instruction Interaction with String Operation May Cause Deadlock Problem: Under the following scenario, combined with a specific alignment of
  • Intel SL3VS | Specification Update - Page 66
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE or IMUL AX, word ptr (opcode 0F AF /r) or (the 16th bit) of AX. This is noticeable when the value in AX after the MOVSX, IMUL or CBW instruction is negative (i.e., bit 15 of AX is a 1). When AX is positive (bit 15 of AX is 0), MOVD
  • Intel SL3VS | Specification Update - Page 67
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE *Note: MOV EAX, EAX is used here in a this section. C69. Livelock May Occur Due to IFU Line Eviction Problem: Following the conditions outlined for erratum C63, if the instruction that is currently being executed from the evicted line must be restarted
  • Intel SL3VS | Specification Update - Page 68
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C70. Selector for the LTR/LLDT Register May Get Corrupted Problem: The internal selector portion of the respective register (TR, LDTR) may get corrupted if, during a small window of LTR or LLDT system instruction execution, the following sequence of
  • Intel SL3VS | Specification Update - Page 69
    at the beginning of this section. C75. APIC Failure at CPU Core/System Bus Frequency of 766/66 MHz Problem: Operation of the Advanced Programmable Interrupt Controller (APIC) with the Celeron processor is problematic at the CPU core/system bus frequency of 766/66 MHz. With the I/O APIC enabled
  • Intel SL3VS | Specification Update - Page 70
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C76. Machine Check Exception may Occur When Interleaving Code Between Different Memory Types Problem Wrong ESP Register Values During a Fault in VM86 Mode Problem: At the beginning of the IRET instruction execution in VM86 mode, the lower 16 bits of the
  • Intel SL3VS | Specification Update - Page 71
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C79. The instruction Fetch Unit (IFU) May Fetch Instructions Based Upon Stale CR3 Data After a Write to CR3 Register Problem: Under a complex set of conditions, there exists a one clock window following a write to the CR3 register where-in it is
  • Intel SL3VS | Specification Update - Page 72
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C82. Incorrect Assertion of THERMTRIP# Signal Problem: The internal control register example workaround circuits shown do not support production motherboard test methodologies that require the use of the processor JTAG/TAP port. Alternative workaround
  • Intel SL3VS | Specification Update - Page 73
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Figure 1 Celeron® on 0.13 Micron Processor 256K Platforms Workaround 2.5V R1 330 ohm R2 510 ohm R4 0 ohm R3 1.3K ohm R5 39 ohm PWRGD PGA370 TCK For Production Boards: Depopulate
  • Intel SL3VS | Specification Update - Page 74
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C83. Under Some Complex Conditions, the Instructions in the shadow of a JMP FAR may be Unintentionally Executed and Retired Problem: If all of the following events happen in sequence it is possible for the system or application to hang or to execute
  • Intel SL3VS | Specification Update - Page 75
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C85. Lock Data Access that Spans Two Pages May Cause the System to Hang Problem: An instruction with lock data access that spans across two pages may, given some rare internal conditions, hang the system. Implication: When this erratum occurs, the
  • Intel SL3VS | Specification Update - Page 76
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C87. The FXSAVE, STOS, or MOVS Instructions May Cause a Store Ordering Violation When Data Crosses a Page with a UC Memory Type Problem: If the data from an FXSAVE, STOS, or MOVS instruction crosses a page boundary from WB to UC memory type and this
  • Intel SL3VS | Specification Update - Page 77
    instruction the processor reports a numeric exception instead of reporting an exception because of a Null segment. If the numeric exception handler tries to access the FST data it will get a #GP fault. Intel on SMM Handler when SMBASE Is Not Aligned Problem: With SMBASE being relocated to a non-
  • Intel SL3VS | Specification Update - Page 78
    INTEL® CELERON® PROCESSOR (rather than WC as specified in IA-32 Intel® Architecture Software Developer's Manual).. Implication: When this erratum occurs, the memory Conditions LTR (Load Task Register) Instruction May Result in System Hang Problem: An LTR instruction may result in a system hang
  • Intel SL3VS | Specification Update - Page 79
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Problem: A load from memory type USWC may get its data internally or floating point state with FSAVE, FNSAVE or FXSAVE before an intervening FP instruction may save uninitialized values for the FPUDataPointer. Implication: When this erratum occurs
  • Intel SL3VS | Specification Update - Page 80
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Implication: This erratum may cause an unexpected stack overflow. Workaround: User mode code should not count on being able to recover from illegal accesses to memory regions protected with supervisor only access when using FP instructions -service
  • Intel SL3VS | Specification Update - Page 81
    ® CELERON® PROCESSOR SPECIFICATION UPDATE Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception) instead of a #GP fault (general protection exception). Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel
  • Intel SL3VS | Specification Update - Page 82
    INTEL® CELERON® PROCESSOR SPECIFICATION for LBR/BTS/BTM will be Incorrect after an Exit from SMM Problem: After a return from SMM (System Management Mode), the CPU would only occur when one of the 3 above mentioned debug support facilities are used. Implication: The value of the LBR, BTS,
  • Intel SL3VS | Specification Update - Page 83
    INTEL® CELERON® PROCESSOR Problem: Under certain conditions as described in the Software Developers Manual section "Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors" the processor single REP MOVS or REP STOS instruction that will execute with fast strings
  • Intel SL3VS | Specification Update - Page 84
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE • INT1 instruction; • Code breakpoint the DR6 BS (Single Step, Tables of Changes C106. Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame Problem: Implication: The ENTER instruction is used to create a procedure stack frame
  • Intel SL3VS | Specification Update - Page 85
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C108: INVLPG Operation for Large (2M/4M) Pages May be Incomplete under Certain Conditions Problem: The INVLPG instruction may not completely invalidate Translation Look-aside Buffer (TLB) entries for large pages (2M/4M) when both of the following
  • Intel SL3VS | Specification Update - Page 86
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C111 Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions Problem: Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H) counts transitions from x87 Floating Point (FP) to MMX™ instructions. Due to this erratum,
  • Intel SL3VS | Specification Update - Page 87
    listed in this section apply to the following documents: • Pentium® II Processor Developer's Manual • P6 Family of Processors Hardware Developer's Manual • Intel® Celeron® Processor Datasheet • Intel Architecture Software Developer's Manual, Volumes 1, 2, and 3 All Documentation Changes will be
  • Intel SL3VS | Specification Update - Page 88
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C2. Executing the SSE2 Variant on a Non-SSE2 Capable Processor In Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference the section for each of the following instructions states that executing the instruction in real or
  • Intel SL3VS | Specification Update - Page 89
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE It should state: "If FOP code compatibility mode is enabled, the FOP is defined as it has always been in previous IA32 implementations (always defined as the FOP of the last non-transparent FP instruction executed before a FSAVE/FSTENV/FXSAVE). If FOP
  • Intel SL3VS | Specification Update - Page 90
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C7. EFLAGS Register Correction The Intel Architecture Software Developer's Manual Intel Architecture Software Developer's Manual, Vol 3: System Programming Guide mechanism on the IA-32 processor on which the CPUID instruction is executed. • PG flag
  • Intel SL3VS | Specification Update - Page 91
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C9. 0x33 Opcode The Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference Appendix A, Table A-2, the opcode corresponding to 0x33 currently states: Gb, Ev It should state: Gv, Ev Also, Page 3-791, XOR-Logical Exclusive OR
  • Intel SL3VS | Specification Update - Page 92
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C12. Errors in Instruction Set Reference The following changes will be made to the Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference: 1. Page 3-586 "PMULUDQ-Multiply Packed Unsigned Doubleword Integers" currently states:
  • Intel SL3VS | Specification Update - Page 93
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE PMOVMSKB (66) Gd, Vdq 5. Page A-10, It should state: PSUBQ Pq, Qq PSUBQ (66) Vdq, Wdq 8. Page B-21, Table B-12, MMX Instruction Formats and Encodings (Contd.). Entry PMADD currently states: PMADD - Packed Multiply add It should state: PMADDWD - Packed
  • Intel SL3VS | Specification Update - Page 94
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE PMULH - Packed multiplication It should state: PMULHW - Packed multiplication, store high word 10. Page B-21, Table B-12, MMX Instruction Formats and Encodings (Contd.). Add instruction PMULHUW : PMULHUW - Packed multiplication, store high word (
  • Intel SL3VS | Specification Update - Page 95
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE 15. Page B-41, Table B-19, Formats and Encodings of the SSE2 SIMD Integer Instruction. Entry PMULL currently states: PMULL - Packed multiplication It should state: PMULLW - Packed multiplication, store low word C13. RSM Instruction Set Summary The Intel
  • Intel SL3VS | Specification Update - Page 96
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C15. DAA-Decimal Adjust AL after Addition The Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference page 3-173 currently states: Operation IF (((AL AND 0FH) > 9) or AF = 1) THEN AL ←AL + 6; CF ←CF OR CarryFromLastAddition; (*
  • Intel SL3VS | Specification Update - Page 97
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C16. DAS-Decimal Adjust AL after Subtraction The Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference, on page 3-175 currently states: Operation IF (AL AND 0FH) > 9 OR AF = 1 THEN AL ←AL - 6; CF ←CF OR CarryFromLastAddition;
  • Intel SL3VS | Specification Update - Page 98
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C17. Omission of Dependency Between BTM and LBR The Intel Architecture Software Developer's Manual, Vol 3: System Programming Guide Chapter 15, Section 5.3, on page 15-15 currently states: 15.5.3. Monitoring Branches, Exceptions, and Interrupts (Pentium
  • Intel SL3VS | Specification Update - Page 99
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C18. I/O Permissions Bitmap Base Addy > 0xDFFF Does not Cause #GP(0) Fault The Intel Architecture Software Developer's Manual The Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference Section 3.2 Instruction Reference under
  • Intel SL3VS | Specification Update - Page 100
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C20. Figure 15-12 PEBS Record Format The Intel Architecture Software Developer's Manual, Vol 3: System Programming Guide Section 15.9.6 " Programming the Performance Counters for Non-Retirement Events" page 15 - 37, Figure 15-12, first row currently
  • Intel SL3VS | Specification Update - Page 101
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C22. Cache Description The Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference Table 3- initialization procedure is compatible with the Pentium 4, Intel Xeon, P6 family, and Pentium processors. Following power up or power
  • Intel SL3VS | Specification Update - Page 102
    of error-reporting banks supported *) IF (P6 Family Processor) THEN FOR error-reporting banks (1 through MAX_BANK_NUMBER) DO IA32_MCi_CTL
  • Intel SL3VS | Specification Update - Page 103
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Example . In addition, when using P6 family processors, the software must set MCi_STATUS registers to 0 when doing a soft-reset. Machine-Check Initialization Pseudocode Check CPUID Feature Flags for MCE and MCA support IF CPU supports MCE THEN IF CPU
  • Intel SL3VS | Specification Update - Page 104
    INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE FOR error-reporting banks (0 through MAX_BANK_NUMBER) DO IA32_MCi_STATUS
  • Intel SL3VS | Specification Update - Page 105
    Pentium® II Processor Developer's Manual • P6 Family of Processors Hardware Developer's Manual • Intel® Celeron® Processor Datasheet • Intel® 64 and IA-32 Architectures Software Developer's Manual 9B DB E2 9B DB E3 9B DD /6 Instruction FCLEX FINIT FSAVE m94/108byte Addition Add "Comments" section
  • Intel SL3VS | Specification Update - Page 106
    of Section 9.12.5 of the Intel Architecture Software Developer's Manual, Volume 3: System Programming Guide: "The MTRRs must be disabled prior to initialization or modification." C4. Non-AGTL+ Output Low Current Clarification In Table 6 of the Intel® Celeron® Processor Datasheet, the note in bold
  • Intel SL3VS | Specification Update - Page 107
    in this section apply to the following documents: • Pentium® II Processor Developer's Manual • P6 Family of Processors Hardware Developer's Manual • Intel® Celeron® Processor Datasheet • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volumes 1, 2A, 2B, 3A and 3B. All Specification
  • Intel SL3VS | Specification Update - Page 108
    TDP values represent the thermal design point required to cool Celeron processors in the platform environment. This replaces column 3 and column 4, Processor Power and Processor Core Power, from Table 37 of the Intel® Celeron® Processor Datasheet. Additional derating of the thermal design power and
  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
Intel
®
Celeron
®
Processor
Specification Update
Release Date: August 2007
Document Number: 243748-051
The Intel
®
Celeron
®
processor may contain design defects or errors known as errata, which may cause the
product to deviate from published specifications. Current characterized errata are documented in this
Specification Update.