Intel T8300 Specifications

Intel T8300 - Core 2 Duo 2.4GHz 800MHz 3MB Socket P Mobile CPU Manual

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  • Intel T8300 | Specifications - Page 1
    Intel® Core™2 Extreme Quad-Core Mobile Processor, Intel® Core™2 Quad Mobile Processor, Intel® Core™2 Extreme Mobile Processor, Intel® Core™2 Duo Mobile Processor, Intel® Core™2 Solo Mobile Processor and Intel® Celeron® Processor on 45-nm Process Specification Update December 2011 Document Number:
  • Intel T8300 | Specifications - Page 2
    with a power source and a network connection. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Intel Core, Intel Centrino, Intel SpeedStep, Intel386, Intel486, Pentium, Pentium Pro, Pentium 4, MMX, and
  • Intel T8300 | Specifications - Page 3
    Contents Preface ...5 Identification Information ...7 Summary Tables of Changes 13 Errata ...21 Specification Changes ...53 Specification Clarifications ...54 Documentation Changes ...56 Specification Update 3
  • Intel T8300 | Specifications - Page 4
    Erratum AZ66-74 October 2008 1.0  Added Erratum AZ75  Added Specification Clarification AZ2 November 2008 1.0  Table 1 added new skus and updated 2009 R step information  Errata table added R step information 1.0  S-SPEC updated for new E and R step in Table 1 April 2009 1.0 
  • Intel T8300 | Specifications - Page 5
    's Manual, Volume 2A: Instruction Set Reference, A-M Intel® 64 and IA-32 Architecture Software Developer's Manual, Volume 2B: Instruction Set Reference, N-Z Intel® 64 and IA-32 Architecture Software Developer's Manual, Document Number/Location 252046 253665 253666 253667 253668 Specification
  • Intel T8300 | Specifications - Page 6
    Software Developer's Manual, Volume 3B: System Programming Guide IA-32 Intel® Architecture Optimization Reference Manual Intel Processor Identification and the CPUID Instruction Application Note (AP-485) Intel® 64 and IA-32 Architectures Application Note TLBs, PagingStructure Caches, and Their
  • Intel T8300 | Specifications - Page 7
    Identification via Programming Interface Intel® Core™2 Extreme Quad-Core Mobile Processor, Intel® Core™2 Quad Mobile Processor, Intel® Core™2 Extreme Mobile Processor, Intel® Core™2 Duo Mobile Processor, Intel® Core™2 Solo Mobile Processor and Intel® Celeron® Processor on 45nm Process stepping
  • Intel T8300 | Specifications - Page 8
    be identified by the following component markings: Figure 1. Processor S-Spec Top-side Markings (Example) MARK EXAMPLE: Group 1 Line 1: Unit Identifier Processor # Group 1 Line 2: FPO SSPEC# Group 2 Line 1: Frequency/L2 Cache/FSB Speed Group 2 Line 2: INTEL (m) © '07 8 Specification Update
  • Intel T8300 | Specifications - Page 9
    Identification Information Table 1. Processor Identification Information Processor # Processor Stepping FSB Freq. (MHz) IDAT Freq.(GHz) HFM TDP (W) L 2 Cache(MB) SSpec# Package CPUID Core Frequency HFM/LFM/ SLFM (GHz) Notes SLAQH T9500 m-FCPGA C-0 000010676h 2.6/1.2/0.8 800 2.8 35 6
  • Intel T8300 | Specifications - Page 10
    Processor # Processor Stepping FSB Freq. (MHz) IDAT Freq.(GHz) HFM TDP (W) L 2 Cache(MB) SSpec# Package CPUID Core Frequency HFM/LFM/ SLFM (GHz) Notes SLB4M P8400 m-FCBGA M-0 000010676h 2.26/1.6/0.8 1066 2.40 25 3 6,11,12 SLB3Q P8400 m-FCPGA M-0 000010676h 2.26/1.6/0.8 1066 2.40
  • Intel T8300 | Specifications - Page 11
    Identification Information Processor # Processor Stepping FSB Freq. (MHz) IDAT Freq.(GHz) HFM TDP (W) L 2 Cache(MB) SSpec# Package CPUID Core Frequency HFM/LFM/ SLFM (GHz) Notes QJNW 723 m-FCBGA R-0 00001067Ah 1.2/(n/a)/(n/a) 800 N/A 10 1 35,13 QJPT SU3300 m-FCBGA R-0 00001067Ah
  • Intel T8300 | Specifications - Page 12
    80-1.25 [VID] 35. Vcc core VID=0.775-1.10 [VID] 36. Vcc core VID=0.900-1.2125/0.850-1.025 V [HFM/LFM]; 0.75-0.95 V [S-LFM] 37. Vcc core VID=0.900-1.2125/0.850-1.025 V [HFM/LFM]; 0.75-0.95 V [S-LFM] 38. Vcc core VID=0.900-1.175/0.850-1.025 V [HFM/LFM]; 0.75-0.95 V [S-LFM] § 12 Specification Update
  • Intel T8300 | Specifications - Page 13
    Summary Tables of Changes Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed CPU steppings. Intel intends to fix some of the errata in a future stepping of the component, and to
  • Intel T8300 | Specifications - Page 14
    ® processor D = Dual-Core Intel® Xeon® processor 2.80 GHz E = Intel® Pentium® III processor F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor I = Dual-Core Intel® Xeon® processor 5000 series J = 64-bit Intel® Xeon® processor MP with 1-MB L2 Cache K = Mobile Intel® Pentium
  • Intel T8300 | Specifications - Page 15
    = Intel® Core™ 2 Duo AX =Quad-Core Intel® Xeon® processor 5400 series AY =Dual-Core Intel® Xeon® processor 5200 series AZ = Intel® Core™2 Extreme Quad-Core Mobile Processor, Intel® Core™2 Quad Mobile Processor, Intel® Core™2 Extreme Mobile Processor, Intel® Core™2 Duo Mobile Processor, Intel® Core
  • Intel T8300 | Specifications - Page 16
    Fix The Processor May bit L2 ECC Errors May be Incorrect AZ18 X X X X No Fix Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher Priority Interrupts/Exceptions AZ19 X X X X No Fix Store Ordering May be Incorrect between WC and WP Memory Type 16 Specification
  • Intel T8300 | Specifications - Page 17
    Fix Performance Monitoring Events for Retired Instructions (C0H) May Not Be Accurate AZ23 X X X X No Fix Returning to Real Mode from SMM with EFLAGS.VM Set May Result in Unpredictable System Behavior AZ24 X X X X No Fix CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal
  • Intel T8300 | Specifications - Page 18
    Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior AZ49 X X X X Plan Fix RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results AZ50 X X X X No Fix Benign
  • Intel T8300 | Specifications - Page 19
    X X X X No Fix A 64-bit Register IP-relative Instruction May Return Unexpected Results AZ77 X X X X No Fix Intel® Trusted Execution Technology ACM Revocation Number SPECIFICATION CHANGES There are no Specification Changes in this Specification Update revision Specification Update 19
  • Intel T8300 | Specifications - Page 20
    SPECIFICATION CLARIFICATIONS AZ1 AZ2 Clarification of Translation Lookaside Buffers (TLBS) Invalidation CPUID Instruction Will Return Brand String With a Missing Letter Number DOCUMENTATION CHANGES There are no Documentation Changes in this Specification Update revision. § 20 Specification
  • Intel T8300 | Specifications - Page 21
    Errata Errata AZ1. EFLAGS Discrepancy on a Page Fault after a Multiprocessor TLB Shootdown Problem: This erratum may occur when the processor executes one of the following read-modifywrite arithmetic instructions and a page fault occurs during the store of the memory operand: ADD, AND, BTC, BTR
  • Intel T8300 | Specifications - Page 22
    Problem: The INVLPG instruction in either A or D bits being set in a . Intel has by Two, Subsequent Loads Problem: When data of Store external memory or L2 written by another core, while the Wrong Program Order Problem: When non Intel® 64 and IA-32 Architectures Software Developer's Manual
  • Intel T8300 | Specifications - Page 23
    Signaling a Code Segment Limit Fault Problem: If code segment limit is set close to the end of a code page, then due to this erratum the memory page Access bit (A bit) may be set for the subsequent Status: For the steppings affected, see the Summary Tables of Changes. Specification Update 23
  • Intel T8300 | Specifications - Page 24
    monitored address range may prevent the actual triggering store to be propagated to the monitoring hardware. Implication: A logical processor executing an MWAIT instruction may not immediately continue program execution if a REP STOS/MOVS targets the monitored address range. Workaround: Software
  • Intel T8300 | Specifications - Page 25
    the Summary Tables of Changes. AZ11. The Processor May Report a #TS Instead of a #GP Fault Problem: A jump to a busy TSS (Task- instruction ends at the last byte of the segment and the next instruction begins at 0x0. Implication: This is a rare condition that may result in a system hang. Intel
  • Intel T8300 | Specifications - Page 26
    until the interrupt enabled flag is finally set, i.e. by STI instruction. Interrupts will remain pending and are not lost. Implication: In this example the processor may allow interrupts to be accepted but may delay their service. Workaround: This non-synchronization can be avoided by issuing an
  • Intel T8300 | Specifications - Page 27
    Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A section "Out-of-Order Stores for String Operations in Pentium 4, Intel Xeon, and P6 Family Processors" the processor performs REP MOVS or REP STOS as fast strings. Due to this erratum fast string REP MOVS/REP STOS instructions
  • Intel T8300 | Specifications - Page 28
    of Changes. AZ19. Store Ordering May be Incorrect between WC and WP Memory Type Problem: According to Intel® 64 and IA-32 Intel Architecture Software Developer's Manual, Volume 3A "Methods of Caching Available", WP (Write Protected) stores should drain the WC (Write Combining) buffers in the
  • Intel T8300 | Specifications - Page 29
    Problem: When the processor is going into shutdown due to an RSM inconsistency failure, EFLAGS, CR0 and CR4 may be incorrect. In addition the EXF4 signal may still be asserted. This may be observed if the processor ) instruction that performs a memory load and has either CR0.EM=1 (Emulation bit set
  • Intel T8300 | Specifications - Page 30
    Instructions (C0H) May Not Be Accurate Problem: The INST_RETIRED performance monitor may miscount retired instructions instructions are not counted.  HLT and MWAIT instructions are not counted. The following instructions instruction. b) RSM from an SMI during a HLT instruction Problem: Intel
  • Intel T8300 | Specifications - Page 31
    LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to 248 May Terminate Early Problem: In 64-bit Mode CMPSB, LODSB, or written, even if the new LVT entry has the mask bit set. If there is no Interrupt Service Routine (ISR) set up for that vector the system . Specification Update 31
  • Intel T8300 | Specifications - Page 32
    Interrupts Problem: Interrupts that are pending prior to the execution of the STI (Set Interrupt Flag) instruction are serviced immediately after the STI instruction is executed. Because of this erratum, if following STI, an instruction that triggers a #MF is executed while STPCLK#, Enhanced Intel
  • Intel T8300 | Specifications - Page 33
    cache lines within the monitored address range. Implication: The logical processor that executed the MWAIT instruction problem requires the use of a data write which spans a cache line boundary. Implication: This erratum may cause loads to be observed out of order. Intel Specification Update 33
  • Intel T8300 | Specifications - Page 34
    comparison to which features are actually supported. Workaround: Software should use the recommended enumeration mechanism described in the Architectural Performance Monitoring section of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3: System Programming Guide. Status
  • Intel T8300 | Specifications - Page 35
    Stop-Grant Special Cycle Problem: According to the FSB (Front Side Bus) protocol specification, no FSB cycles should be issued by the processor once a Stop-Grant special cycle has been issued to the bus. If xTPR update transactions are enabled by clearing the IA32_MISC_ENABLES[bit 23] at the time
  • Intel T8300 | Specifications - Page 36
    Cache Problem: A livelock may be observed in rare conditions when instruction fetch causes multiple level one data cache snoops. Due to this erratum, a livelock may occur. Intel instruction cache, and the noncacheable address is fetched in the IFU, the processor memory types, Intel has strongly
  • Intel T8300 | Specifications - Page 37
    Field Problem: As specified in Section, "VM Exits Induced by the TPR Shadow", in the Intel® 64 and IA32 Architectures Software Developer's Manual, Volume 3B, a VM exit occurs immediately after any VM entry performed with the "use TPR shadow", "activate secondary controls", and "virtualize APIC
  • Intel T8300 | Specifications - Page 38
    Intel does not support the use of cacheable and WC memory type aliasing, and WC operations are defined as weakly ordered. Status: For the steppings affected, see the Summary Tables of Changes. AZ43. VM Exit Caused by a SIPI Results in Zero Being Saved to the Guest RIP Field in the VMCS Problem
  • Intel T8300 | Specifications - Page 39
    Cause the Processor to Hang Problem: Under some rare conditions, when multiple streaming load instructions (MOVNTDQA) are mixed with non-streaming loads that split across cache lines, the processor may hang. Implication: Under the scenario described above, the processor may hang. Intel has not
  • Intel T8300 | Specifications - Page 40
    : This erratum may lead to livelock, shutdown or other unexpected processor behavior. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 40 Specification Update
  • Intel T8300 | Specifications - Page 41
    Not Cause a Triple Fault Shutdown Problem: According to the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, "Exception and Interrupt Reference", if another exception occurs while attempting to call the double-fault handler, the processor enters shutdown mode. Due to this
  • Intel T8300 | Specifications - Page 42
    THERMTRIP# after Receiving a Warm Reset Problem: Some processors may unexpectedly assert a false THERMTRIP# after a warm reset under certain environmental and operating conditions. Intel has observed this on a limited number of parts when they are operating at a core-to-bus ratio different from
  • Intel T8300 | Specifications - Page 43
    Errata AZ53. Short Nested Loops That Span Multiple 16-Byte Boundaries May Cause a Machine Check Exception or a System Hang Problem: Under a rare set of timing conditions and address alignment of instructions in a short nested loop sequence, software that contains multiple conditional jump
  • Intel T8300 | Specifications - Page 44
    , or system. Workaround: As recommended in the IA32 Intel® Architecture Software Developer‟s Manual, the use of MOV SS/POP SS in conjunction May be Serviced before Higher Priority Interrupts/Exceptions and May Push the Wrong Address Onto the Stack Problem: Normally, when the processor encounters
  • Intel T8300 | Specifications - Page 45
    an interrupt may be delayed by one instruction. Workaround: VMM software should follow the guidelines given in the section "Handling VM Exits Due to Exceptions" of Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide. Status: For the steppings affected
  • Intel T8300 | Specifications - Page 46
    only occur if the IRET instruction is returning from CPL3 code to Intel® Deep Power-Down State Problem: Thermal interrupts are ignored while the processor is in Intel Deep Power-Down State as well as during a small window of time while exiting from Intel Deep Power-Down State. During this window
  • Intel T8300 | Specifications - Page 47
    Intel® 64 and IA-32 Architectures Software Developer‟s Manual Volume 3B: System Programming Guide, Part 2. (The exit reason will be 80000021H and the exit qualification will be zero.) Note that the FREEZE_WHILE_SMM_EN bit Virtual-APIC Page Problem: When XFEATURE_ENABLED_MASK register (XCR0) bit
  • Intel T8300 | Specifications - Page 48
    Implication: If software programs a value in IA32_LSTAR to be used by the SYSCALL instruction and the processor subsequently receives an INIT reset, the SYSCALL instructions will not behave as intended. Intel has not observed this erratum in any commercially available software. Workaround: It is
  • Intel T8300 | Specifications - Page 49
    Address when an Exception/Interrupt Occurs in 64-bit Mode Problem: An exception/interrupt event should be transparent to the LBR (Last Branch Record), BTS (Branch Trace Store) and BTM (Branch Trace Message) mechanisms. However, during a specific boundary condition where the exception/interrupt
  • Intel T8300 | Specifications - Page 50
    of the bottom two bits of the CS segment register will have no impact unless software explicitly examines the CS segment register between enabling protected mode and the first far JMP. Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide, Part 1, in the
  • Intel T8300 | Specifications - Page 51
    execute before older stores. Intel has not observed this Problem: When two logical processors are accessing the same data that is crossing a cacheline boundary without serialization, with a specific set of processor XRSTOR instruction to cause a general-protection exception when any of the bits [63
  • Intel T8300 | Specifications - Page 52
    affected, see the Summary Tables of Changes. AZ76. A 64-bit register IP-relative instruction may Return unexpected Results Problem: Under an unlikely and complex sequence of conditions in 64-bit mode, a register IPRelative instruction may be incorrect. Implication: A register IP-relative
  • Intel T8300 | Specifications - Page 53
    Specification Changes Specification Changes There are no specification changes for this specification update revision. § Specification Update 53
  • Intel T8300 | Specifications - Page 54
    algorithms. AZ2. 54 CPUID Instruction Will Return Brand String With a Missing Letter The Specification Clarification listed in this section applies to the following documents:  Intel® Core™2 Duo Processors, Intel® Core™2 Solo Processors and Intel® Core™2 Extreme Processors on 45-nm Process
  • Intel T8300 | Specifications - Page 55
    Specification Clarifications Intel collateral will continue to show the correct and full processor number (with the first letter „S‟ or letter „X‟). Table 1. Documentation Clarification Processor Number in Datasheet Processor Number in Brand String Displayed SP9400 SP9300 SL9400 SL9300 SU9400
  • Intel T8300 | Specifications - Page 56
    Documentation Changes Documentation Changes There are no documentation changes for this specification update revision. § 56 Specification Update
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Intel
®
Core™2 Extreme Quad
-Core Mobile
Processor,
Intel
®
Core™2 Quad Mobile Processor,
Intel
®
Core™2 Extreme
Mobile Processor,
Intel
®
Core™2 Duo
Mobile Processor,
Intel
®
Core™2 Solo
Mobile
Processor and
Intel
®
Celeron
®
Processor
on 45-nm Process
Specification Update
December 2011
Document Number:
320121-008