Acer AL2032W AL2032W Service Guide - Page 36

SCHEMATIC DIAGRAM Main Board Circuit Chapter 7 +1.8V_CORE 58 VF22u25/ C 57 FV22u25/ C 147 F01u6./ C 154 F01u6./ C 150 F01u6./ C 141 F01u6./ C 138 F01u6./ C 135 F01u6./ C 140 F01u6./ C 139 F01u6./ C 137 F01u6./ C 136 F01u6./ C 122 F01u6./ C 145 F01u6./ C 153 F01u6./ C 146 F01u6./ C GND +2.5V_DDR +1.8V_CORE +3.3V_I/O_MALIBU +3.3V_LBADC +2.5V_DDR +1.8V_DVI +3.3V_LVDSB +3.3V_LVDSA +3.3V_LVDS FSVREF +3.3V_DVI +1.8V_ADC+3.3V_ADC +3.3V_PLL 37 VF22u25/ C V25/ 45 F22u C 124 F01u6./ C 125 F01u6./ C 123 F01u6./ C GND 129 F01u6./ C 121 F01u6./ C 120 F01u6./ C 119 F01u6./ C 130 F01u6./ C 116 F01u6./ C 128 F01u6./ C 127 F01u6./ 126 F01u6./ 40 F01u6./ C 118 F01u6./ CC C 42 F01u6./ C +3.3V_I/O_MALIBU 46 C VF22u25/ 55 C FV22u25/ 164 F01u6./ C 167 F01u6./ C 172 F01u6./ C 6/ 173 F01u. C 134 F01u6./ C 117 F01u6./ C 115 F01u6./ C 151 F01u6./ C 158 F01u6./ C 160 F01u6./ C 163 F01u6./ C GND +1.8V_DVI +3.3V_DVI 6/ 161 F01u. C 6/ 159 F01u. C 156 F01u6./ C 6/ 152 F01u. C GND V25/ 54 C F22u 157 F01u6./ C GND 6/ 143 F01u. C 149 F01u6./ C 6/ 155 F01u. C 162 F01u6./ C R170 0/6/NC R171 0/6/NC RX0+ RX0RX1+ RX1RX2+ RX2RXC+ RXC- +3.3V_DVI R54 249R/6 1% TXD R131 0/6 RXD R132 0/6 +3.3V_PLL +3.3V_PLL 22pF/6 C68 C67 22pF/6 3 VGA_SCL 3 VGA_SDA 3 BLUE3 BLUE+ 3 GREEN3 GREEN+ 3 RED3 RED+ 3 SOG 3 AHS 3 AVS 17 K 17 U 11 U L16 T16 17 T L11 10 K K16 T11 16 U 10 U K11 23 K 17 D 23 D 4 CA 6 AC 8 CA 10 AC 22 D A4 A 4 W B4 A 4 Y 13 C 23 H 23J 23 M 23 P L23 T23 23 V 23 R 23 Y A23 A B23 A 23 CA 23 W F23 E23 12 12 13 20 22 21 CA AD D A DCC AAA E17 A N4 _18. E R O _18. E R O _18. E R O _18. E R O _18. E R O _18. E R O _18. E R O _18. E R O _18. E R O _18. E R O _18. E R O _18. E R O _18. E R O LL D_ A18 CCCCCCCCCCCCCD N3 DVI_SCL D A8 DVI_SDA V B8 RX0+ _33. OI _33. OI _33. OI _33. OI _33. OI _33. OI _33. OI _33. OI _33. OI _33. OI _33. OI 33D BACL _25. _25. _25. _25. _25. _25. _25. _25. _25. _25. _25. _25. _25. _25. _25. SF FS SF FS SF FS SF FS SF FS SF FS SF FS SF _33. _33. _33. SB SB SB DVL VDL DVL _33. _33. _33. SA SA SA DVL VDL DVL S VD_L 33 D D VD A9 RX0- B9 RX1+ A10 RX1- B10 RX2+ A6 RX2- B6 RXC+ D5 RXC- C5 NO_CONNECT B11 NO_CONNECT REXT B1 B2 BLUEC1 BLUE+ C2 GREEND1 GREEN+ D2 REDC3 RED+ A1 SOG N2 NO_CONNECT N1 VGA_SCL L4 VGA_SDA L3 AHSYNC R4 AVSYNC EXTCLK X1 14.318MHz Route (VIN1/ADC_IN1, ADC1_RETURN) and (VIN2/ADC_IN2, ADC2_RETURN) as differential tracks close to each other and ground the return track of each pair very close to the Malibu D12 ball and ground pin Optional Filter Caps in between a pair on LBADC differential tracks close to the Malibu chip CN3 +5V 1 2 3 4 4606-04-04P-R/NS GND TXD RXD R77 3K3/6 GND XTAL TCLK ACS_RSET_HD R78 10K/6 GND R37 10K/6 7 PWM0 7 PWM1 GND PWM0 T106 T105 PWM1 GND SCART_FUNC SCART_RGB_CON GND T101 T103 T104 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 T102 LLC_VPC G4 G3 XTAL F1 TCLK K3 NO_CONNECT K2 NO_CONNECT ACS_RSET_HD C19 B19 VRED0 A19 VRED1 D18 VRED2 C18 VRED3 B18 VRED4 A18 VRED5 C17 VRED6 VRED7 A23 C22 VGRN0 B22 VGRN1 A22 VGRN2 D21 VGRN3 C21 VGRN4 B21 VGRN5 A21 VGRN6 VGRN7 B25 A25 VBLU0 D24 VBLU1 C24 VBLU2 B24 VBLU3 A24 VBLU4 C23 VBLU5 B23 VBLU6 VBLU7 A20 B20 VCLK C20 VODD D19 VVS D20 VHS_CSYNC B17 VDV VCLAMP C26 C25 PWM0 D26 PWM1 D25 PWM2 OCM_TIMER1 A12 B12 LBADC_IN3 C12 LBADC_IN2 D12 LBADC_IN1 LBADC_RETURN C16 B16 SVDATA0 A16 SVDATA1 D15 SVDATA2 C15 SVDATA3 B15 SVDATA4 A15 SVDATA5 D14 SVDATA6 SVDATA7 A17 A14 SVDV B14 SVODD C14 SVVSYNC D16 SVHSYNC SVCLK M1 M2 OCM_UDO OCM_UDI MSTR_SDA MSTR_SCL K1 /RESET M4 /RESET IR1 M3 IR1 GND IR0 P4 IR0 MSTR_SCL MSTR_SCL MSTR_SDA P3 MSTR_SDA FSVREF C38 0.1uF/6 C39 0.1uF/6 GND +1.8V_ADC C63 C62 0.1uF/6 0.1uF/6 GND +3.3V_ADC C70 C168 22uF/25V 0.1uF/6 C175 0.1uF/6 C171 0.1uF/6 C169 0.1uF/6 +3.3V_PLL GND C77 2252VuF/25V177 F01u6./ C 174 F01u6./ C 176 F01u6./ C 178 F01u6./ C 165 F01u6./ C 170 F01u6./ C 166 F01u6./ C GND +3.3V_LVDSA +3.3V_LVDS C44 C131 22uF/25V 0.1uF/6 25V C133 0.1uF/6 C132 0.1uF/6 C47 0.1uF/6 GND +3.3V_LVDSB GND 6 /OCM_WE 6 /OCM_RE 6 /ROM_CS /OCM_WE /OCM_RE T107/OCM_CS T108 T109 T110 T111 R3 R2 /OCM_WE R1 /OCM_RE L1 /ROM_CS L2 /OCM_INT2 P2 /OCM_INT1 P1 /OCM_CS2 T4 /OCM_CS1 /OCM_CS0 6 OCMADDR[0..19] OCMADDR19 T3 OCMADDR19 OCMADDR18 T2 OCMADDR18 OCMADDR17 T1 OCMADDR17 OCMADDR16 U4 OCMADDR16 OCMADDR15 U3 OCMADDR15 OCMADDR14 U2 OCMADDR14 OCMADDR13 U1 OCMADDR13 OCMADDR12 V4 OCMADDR12 OCMADDR11 V3 OCMADDR11 OCMADDR10 V2 OCMADDR10 OCMADDR9 V1 OCMADDR9 OCMADDR8 W3 OCMADDR8 OCMADDR7 W2 OCMADDR7 OCMADDR6 OCMADDR5 OCMADDR4 OCMADDR3 WY13 Y2 Y1 OCMADDR6 OCMADDR5 OCMADDR4 OCMADDR3 OCMADDR2 AA3 OCMADDR2 OCMADDR1 AA2 OCMADDR1 OCMADDR0 AA1 OCMADDR0 6 OCMDATA[0..7] KEY 1 KEY 2 KEY 3 RIGHT LEFT T112 T113 T114 OCMDATA7 OCMDATA6 OCMDATA5 OCMDATA4 OCMDATA3 OCMDATA2 OCMDATA1 OCMDATA0 AB3 AB2 OCMDATA15 AB1 OCMDATA14 AC3 OCMDATA13 AC2 OCMDATA12 AC1 OCMDATA11 AD1 OCMDATA10 AE1 OCMDATA9 AF1 OCMDATA8 AD2 OCMDATA7 AE2 OCMDATA6 AF2 OCMDATA5 AD3 OCMDATA4 AE3 OCMDATA3 AF3 OCMDATA2 AD4 OCMDATA1 OCMDATA0 J24 25 W 6 8 9 10 DDDD 11 10 9 8 6 CCCCC 3 A A4 2 A 3 B 3 D E3 4 F F2 1 G 3 H 1 H J3 1J EF EF VR RV SF FS _18I. _18I. _18I. _18I. VVVV DDDD _33I. _33I. _33I. _33I. _33I. VVVVV DDDDD _18. _18. _33. _33. _33. _33. CC CCCC DA AD AD DA AD DA PLL R_ 33 A D VD P_LL A33 D DV PLL F_ A33 D VD S D DS_ A33 D D V S D SD_ A33 D D V S D D D_ A33 D DV S D D D_ A33 D VD FSDATA0 FSDATA1 FSDATA2 FSDATA3 FSDATA4 FSDATA5 FSDATA6 FSDATA7 FSDATA8 FSDATA9 FSDATA10 FSDATA11 FSDATA12 FSDATA13 FSDATA14 FSDATA15 FSDATA16 FSDATA17 FSDATA18 FSDATA19 FSDATA20 FSDATA21 FSDATA22 FSDATA23 FSDATA24 FSDATA25 FSDATA26 FSDATA27 FSDATA28 FSDATA29 FSDATA30 FSDATA31 FSADDR0 FSADDR1 FSADDR2 FSADDR3 FSADDR4 FSADDR5 FSADDR6 FSADDR7 FSADDR8 FSADDR9 FSADDR10 FSADDR11 FSCLKp FSCLKn FSDQS FSDQM0 FSDQM1 FSDQM2 FSDQM3 FSWE FSCAS FSRAS FSCKE FSBKSEL0 FSBKSEL1 GPIO_G06_B0 GPIO_G06_B1 GPIO_G06_B2 GPIO_G06_B3 A3+ A3AC+ AC- GPIO_G05_B0 GPIO_G05_B3 A2+ A2A1+ A1A0+ A0- GPIO_G04_B0 GPIO_G04_B1 GPIO_G04_B2 GPIO_G04_B3 GPIO_G04_B4 GPIO_G04_B5 GPIO_G04_B6 GPIO_G04_B7 GPIO_G07_B0 GPIO_G07_B1 GPIO_G07_B2 GPIO_G07_B3 GPIO_G07_B4 GPIO_G07_B5 GPIO_G07_B6 GPIO_G07_B7 LVDS_SHIELD[0] LVDS_SHIELD[1] LVDS_SHIELD[2] LVDS_SHIELD[3] B3+ B3BC+ BC- LVDS_SHIELD[4] LVDS_SHIELD[5] B2+ B2B1+ B1B0+ B0- DCLK GPIO_14/DHS GPIO_15/DVS GPIO_16/DEN GPIO_G08_B5/JTAG_RESET GPIO_G08_B4/JTAG_TDO GPIO_G08_B3 GPIO_G08_B2/JTAG_TDI GPIO_G08_B1/JTAG_MODE GPIO_G08_B0/JTAG_CLK GPIO_G09_B5 GPIO_G09_B4 GPIO_G09_B3 GPIO_G09_B2 GPIO_G09_B1 GPIO_G09_B0 PPWR PBIAS NO_CONNECT OEXTR D_GND C52 C144 22uF/25V 0.1uF/6 25V C142 0.1uF/6 C148 0.1uF/6 GND +5V +3.3V_ADC LL D_ D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D D N G_ D SA18 VS A13 14 U L15 15 M 15 P 15 R 15 U 11 M 11 N 11 R 16 P 17 N 10 N 10 R K12 L12 13 M 12 M 12 N 12 P 12 T 12 U L13 13 N 13 R L10 T13 T10 K14 L14 14 N P14 B13 25 K DDDDDDDDDDDDDDDDDDDD NNNNNNNNNNNNNNNNNNNN G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ G_ DDDDDDDDDDDDDDDDDDDD 14 T K15 15 N 15 T 16 M 16 N 16 R 12 R K13 13 P 13 U 14 M 14 R 11 P 10 M 17 M 17 P 17 R P10 L17 DDD NNN G_ G_ G_ SB SB SB 13VDL14DVL15VDL CCC AAA SSS DDD V_L V_L V_L SAA33 SAA33 SAA33 19VS20VS19VS AC C A AD S VD_L 33 SD 17VS D A SS SS EVF EFV VR RV SF FS 26 K 24 W D N G D_ D N GA_ D N GA_ D N G D_ D N GA_ D N GA_ D N GA_ CCCCCCC DA AD DA AD DA AD DA B4 4 D 2 E A5 1 E 4 C E4 DDDDDDD NNNNNNN GV_I GV_I GV_I GV_I GV_I GV_I GV_I DDDDDDD A7 7 B 7 C 7 D A11 11 D B5 D N G_ C D BAL 13 D LL P R_ SA33 P_LL 33 DS PF_LL SA33 S D DS_ SA33 S D SD_ 33 SD S D D D_ SA33 S D D D_ 33 SD VS VS VS VS VS VS VS 3 F 2 G 4 H 2 H 4J J2 K4 R150 R151 10K/6 GND GND U5 GM1601 416PBGA E24 E25 FSDATAU0 E26 FSDATAU1 G26 FSDATAU2 G24 FSDATAU3 H26 FSDATAU4 H24 FSDATAU5 J25 FSDATAU6 T26 FSDATAU7 R25 FSDATAU8 P24 FSDATAU9 P26 FSDATAU10 N24 FSDATAU11 N26 FSDATAU12 M25 FSDATAU13 L24 FSDATAU14 L25 FSDATAU15 M26 FSDATAU16 M24 FSDATAU17 N25 FSDATAU18 N23 FSDATAU19 P25 FSDATAU20 R26 FSDATAU21 R24 FSDATAU22 K24 FSDATAU23 J26 FSDATAU24 H25 FSDATAU25 G23 FSDATAU26 G25 FSDATAU27 F24 FSDATAU28 F25 FSDATAU29 F26 FSDATAU30 FSDATAU31 AD25 AD26 FSADDRU0 AC24 FSADDRU1 AC25 FSADDRU2 AB26 FSADDRU3 AA24 FSADDRU4 AA25 FSADDRU5 AA26 FSADDRU6 Y24 FSADDRU7 AB25 FSADDRU8 AC26 FSADDRU9 AB24 FSADDRU10 FSADDRU11 U24 U23 FSCLKU+ FSCLKU- L26 FSDQSU T25 U25 FSDQMU0 U26 FSDQMU1 T24 FSDQMU2 V26 FSDQMU3 V25 /FSWEU V24 /FSCASU W26 /FSRASU Y25 FSCKEU Y26 FSBKSELU0 FSBKSELU1 FSDATA[0..31] FSDATAU0 FSDATAU1 FSDATAU2 FSDATAU3 FSDATAU4 FSDATAU5 FSDATAU6 FSDATAU7 FSDATAU10 FSDATAU11 FSDATAU9 FSDATAU8 FSDATAU14 FSDATAU15 FSDATAU12 FSDATAU13 FSDATAU16 FSDATAU17 FSDATAU18 FSDATAU19 FSDATAU20 FSDATAU21 FSDATAU22 FSDATAU23 FSDATAU28 FSDATAU26 FSDATAU25 FSDATAU24 FSDATAU29 FSDATAU30 FSDATAU31 FSDATAU27 RN11 1 33 2 3 4 RN12 1 33 2 3 RN74 1 33 2 3 4 RN6 1 33 2 3 RN143 1 33 2 3 4 RN9 1 33 2 3 4 RN5 1 33 2 3 RN44 1 33 2 3 4 FSADDRU6 RN3 1 FSADDRU5 33 2 FSADDRU4 3 FSADDRU9 4 FSBKSELU1 RN2 1 FSBKSELU0 33 2 FSADDRU8 3 FSADDRU7 4 8 FSDATA0 7 FSDATA1 6 FSDATA2 5 FSDATA3 8 FSDATA4 7 FSDATA5 6 FSDATA6 5 8 FSDATA7 7 FSDATA10 6 FSDATA11 5 FSDATA9 FSDATA8 8 FSDATA14 7 FSDATA15 6 FSDATA12 5 8 FSDATA13 7 FSDATA16 6 FSDATA17 5 FSDATA18 8 FSDATA19 7 FSDATA20 6 FSDATA21 5 FSDATA22 FSDATA23 8 FSDATA28 7 FSDATA26 6 FSDATA25 5 8 FSDATA24 7 FSDATA29 6 FSDATA30 5 FSDATA31 FSDATA27 8 FSADDR6 7 FSADDR5 6 FSADDR4 5 FSADDR9 8 FSBKSEL1 7 FSBKSEL0 6 FSADDR8 5 FSADDR7 FSADDRU0 R36 FSADDRU1 FSADDRU11 RN8 FSADDRU10 33 FSADDRU3 FSADDRU2 R35 1 2 3 4 FSCLK+ FSCLK- R34 33R/6 33R/6 33R/6 8 7 6 5 FSADDR0 FSADDR1 FSADDR11 FSADDR10 FSADDR3 FSADDR2 FSCLK+ 5 FSCLK- 5 FSDQS 5 FSDATA[0..31] 5 FSBKSEL1 5 FSBKSEL0 5 FSADDR[0..11] 5 CN8 RX2RX1RX0RXC- 1 2 31 24 53 46 75 68 9 7 8 10 Y0 Y2 Y4 Y6 LLC_VPC 11 9 10 12 13 11 12 14 15 13 14 16 17 15 16 18 19 17 18 20 21 19 20 22 V5IR SCART_FUNC SCART_RGB_CON nY C OEN nVDSW_SEL nRESET DVI DETECT CARD DETECT TVBOX_DETECT IR1 23 25 27 29 31 33 35 3379 41 43 21 23 25 27 29 31 33 35 37 39 41 43 22 24 26 28 30 32 34 36 38 40 42 44 24 26 28 30 32 34 36 38 40 42 44 V12 1841 44P GND /FSWEU /FSRASU /FSCASU FSCKEU FSDQMU0 FSDQMU3 FSDQMU1 FSDQMU2 RN10 1 33 2 3 4 RN1 1 33 2 3 4 8 /FSWE 7 /FSRAS 6 /FSCAS 5 FSCKE 8 FSDQM0 7 FSDQM3 6 FSDQM1 5 FSDQM2 /FS/WFSERA5S 5 /FSCAS 5 FSCKE 5 FSDQM[0..3] 5Place Series term ination resistors on all address and control lines (RN601,RN603,RN605) very close to U600 Unloaded trace im pedance on this interface is 90 Ohm Loaded trace im pedace w ith DRAM load is 65 Ohm (for 2.5 inch total trace length) RX2+ RX1+ RX0+ RXC+ Y1 Y3 Y5 Y7 KEY 1 KEY 2 KEY 3 MSTR_SCL MSTR_SDA TT_I2CSCL TT_I2CSDA CARD_RESET ADO_L 8 ADO_R 8 GND AGND AC18 AD18 AE18 AF18 AE19 AF19 TXA3+ AE20 TXA3- AF20 TXAC+ TXAC- AD21 AD22 AE21 AF21 TXA2+ AE22 TXA2- AF22 TXA1+ AE23 TXA1- AF23 TXA0+ TXA0- AD23 AD24 MENU AE24 AF24 AF25 AF26 AE25 AE26 SEL PWR DOWN UP LED_G LED_R ADO_C AE8 AF8 AC9 nY COEN nVDSW_SEL nRESET AD9 AE9 AF9 AD10 CARD_RESET AE10 TUNER12V_KEY AF10 AC11 AD11 AE11 AF11 AF12 TXB3+ TXB3- AE12 AF13 TXBC+ TXBC- Place Series term ination resistors on bidirectional lines-DATA and DQS (RN600,RN602,RN604,RN606,R605) m idw ay betw een U600 anf U700 Max trace length on this interfce is 2.5 inches Minim ize trace length difference betw een DQS and data and among the data lines R603, R604 very close to U600 FSCLK+, FSCLK- should be routed like a differentail pair +3.3V_DIG R173 +3.3V_DIG 10K/6 ADO_C 8 R128 R33 10K/6 10K/6 DVI DETECT CARD DETECT TUNER12V_KEY 7 +3.3V_DIG R172 10K/6 TVBOX_DETECT AE13 AD14 AF14 TXB2+ AE14 AF15 TXB2TXB1+ AE15 TXB1- AF16 TXB0+ AE16 TXB0- AC7 AF17 AD16 AD7 T115 T116 R48 0/6 +3.3V_DIG R59 10K/6 MUTE MUTE 8 +3.3V_DIG AD8 AF7 JTAG_TRST R52 2K7/6 AE7 AF6 AE6 AD6 AF5 AE5 AD5 TT_I2CSDA TT_I2CSCL R63 10K/6 +3.3V_DIG AC5 AF4 VGA_CAB AE4 T117 VGA_CAB 3 +5V +3.3V_DIG R174 R175 +3.3V_LVDS R15 10K/6/NC R129 0/6/NC TXA0TXA1TXA2- TXACTXA3TXB0- TXB1TXB2TXBCTXB3- R130 0/6/NC R16 0/6/NC LCDVCC PANEL_VCC CN2 1 2 31 53 2 4 4 6 75 68 9 11 7 9 8 10 10 12 13 15 17 19 11 13 15 17 12 14 16 18 14 16 18 20 21 23 25 27 19 21 23 25 20 22 24 26 22 24 26 28 29 27 29 28 30 30 1841 30P GND A26 B26 AC17 AC16 AD15 PPWR PBIAS OEXTR R42 GND PPWR 7 PBIAS 7 3K3/6 GND +3.3V_DIG MSTR_SCL MSTR_SDA 0/6 0/6/NC GND R82 R81 2K7/6 2K7/6 UR784 8 7 6 5 VCC WP SCK SI 0/6 A0 A1 A2 VSS 1 2 3 4 24LC32-SN GND SOIC8 GND I2C address: A2H and A3H R85 0/6/NC PANEL_VCC V25/ 12 F22u C 11 C F01u6./ GND GND +5V 3 C76 C78 C80 C C V OUT 1 /RESET /RESET 0.1uF/6 0.1uF/6 0.1uF/6 GND D N G U8 MAX809_0 2 TXA0+ TXA1+ TXA2+ TXAC+ TXA3+ TXB0+ TXB1+ TXB2+ TXBC+ TXB3+ LCDVCC LCDVCC GND +3.3V_LVDS C RNK14106// 13 R C N06// GND 10K/6 LED_G LED_R R152 4K7/6 3 2 Q12 MMBT3904L R153 4K7/6 2 3 Q13 1 MMBT3904L 1 MENU SEL PWR DOWN UP RIGHT LEFT 154 K336/ R 6/ 155 K33 R 6/ 156 K33 R 6/ 157 K33 R 6/ 158 K33 R 159 K336/ 160 K336/ RR 98 F01u6./ C 193 F01u6./ C 194 F01u6./ C 195 F01u6./ C 196 F01u6./ C 197 C F01u6./ 198 C F01u6./ less R94 to CN6 pin 11 R101,R103 net swap CN5 R161 1K/6 R162 1K/6 10 R163 1K/6 R164 1K/6 R165 1K/6 R166 1K/6 R167 1K/6 R168 220R/6 R169 220R/6 9 8 7 6 5 4 3 2 1 4501-10-10P-R TO BUTTON BOARD 2.0mm pitch GND PROJECT : M0TW Junction from A change to B 90° E&T GND 4607-11Pin Quanta Computer Inc. Title 04. gm1601 Size Document Number Rev M0TW A 04. gm1601 Date: Tuesday , September 14, 2004 Sheet 4 of 8 - 36 -