Acer Aspire 7230 Aspire 7230/7530/7530G Service Guide - Page 165

Check sector 11h 17 for Boot Record Volume

Page 165 highlights

POST Code 0x8B 0x95 0x92 0xB6 0x98 0x93 0xD9 0x9C 0xC7 0x9E 0xA0 0xA2 0xA4 0xDB 0xE2 0xC2 0xBA 0xC3 0xA8 0xAA 0xE1 0xAC 0x8F 0x91 0x9F 0xD7 0xAE 0xB0 0xB2 Function Setup interrupt vector and present bit in Equipment byte. 1. Check CMOS for CD-ROM drive present 2. Activate the drive by checking for media present 3. Check sector 11h (17) for Boot Record Volume Descriptor 4. Check the boot catalog for validity 5. Pick a boot entry 6. Create a Specification Packet Jump to UserPatch2. If password on boot is enabled, a call is made to Setup to check password. If the user does not enter a valid password, Setup does not return. Search for option ROMs. Rom scan the area from C800h for a length of BCP_ROM_Scan_Size (or to E000h by default) on every 2K boundary, looking for add on cards that need initialization. Build the MPTABLE for multi-processor boards IPMI late init Set up Power Management. Initiate power management state machine. Late note dock init Enable hardware interrupts Setup time tick for current date/time Setup Numlock indicator. Display a message if key switch is locked. Initialize typematic rate StrongROM Test OEM security key test Write PEM errors. Initialize the SMBIOS header and sub-structures. Display PEM errors. Overwrite the "Press F2 for Setup" prompt with spaces, erasing it from the screen. Scan the key buffer to see if the F2 key was struck after keyboard interrupts were enabled. If an F2 keystroke is found, set a flag. Start Periodic Timer (TC Subscribe) Check if "Enter SETUP" is pressed. Count the number of ATA drives in the system and update the number in bdaFdiskcount. Configure the local bus IDE timing register based on the drives attached to it. Check the total number of Fast Disks (ATA and SCSI) and update the bdaFdiskCount. Check if FirstWare HPA exists Clear ConfigFailedBit and InPostBit in CMOS. Check for errors and decide if needs to run Setup. Change status bits in CMOS and/or the TrustedCore data area to reflect the fact that POST is complete. Phase LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT LBT Chapter 4 Component Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core 155

We apologize, but we cannot currently deliver this PDF manual by request of the manufacturer.

We apologize for any inconveniece.