Acer Aspire 7730ZG Aspire 7730/7730G/7730Z/7730ZG Service Guide - Page 157

POST Code 0xF3 0xFZ 0xF5 0xFA 0xFB 0xA0xx 0xA4xx 0xE5 0xE6 Function #define MEM_ERR_RCVEN_FINDCENTER (CalibrateRcvenForGroup) #define MEM_ERR_TYPE (S11, S04) #define MEM_ERR_RAWCARD (S11) #define MEM_ERR_SFF (ProgWrioDll) #define MEM_ERR_THERMAL (ProgramThrottling) Launch BIOS ACMSclean Launch BIOS ACMScheck Wait for ME ready ME Ready Phase PEI PEI PEI PEI PEI PEI PEI DXE DXE Core POST Codes The following table details the core POST codes and functions used in the POST. POST Code 0x00 0x01 0x02 0xEE 0xEF 0xnn 0x11 0x22 0x33 0x44 0x88 0x80 0x82 0x84 0x86 0x88 0x8A 0x8C 0x8F 0x90 0xCC 0x20 0x21 0x22 0x23 0x80 0x81 Function Early Microcode update for CAR Enable CAR CAR Done, initial stack unknown CPU ID to load uCode unknown DT CPU to load uCode File count found in a volume Debug Test driver for debug test PPI 1 (If install debugTest driver) Debug Test driver for debug test PPI 2 (If install debugTest driver) Debug Test driver for debug test PPI 3 (If install debugTest driver) Entry point of loadfile Entry point of apMuLoader A PEIM found PEIM not dispatched yet PEIM satisfies depex Image loaded but fail on security Executing a PEIM Processing notify event for newly installed PPI Handing off to next phase (DXE) Fail to hand off to next phase, system halt All PEIM dispatched! Going to DxeIpl AP Micro-code update S3 resume entry Start running Boot-time bootscripts Start running Run-time bootscripts End of S3 resume, jump back to Waking vector Initialize the chipset Initialize the bridge Phase CEI / SEC CEI / SEC CEI / SEC CEI / SEC CEI / SEC PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI S3 resume S3 resume S3 resume S3 resume Crisis Recovery Crisis Recovery Chapter 4 Component chipset/MRC chipset/MRC chipset/MRC chipset/MRC chipset/MRC chipset/TXT chipset/TXT HECI/iAMT HECI/iAMT Component Core Core Core CPU CPU Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core 147