Fujitsu MPB3043AT Product Manual

Fujitsu MPB3043AT - Desktop 4.3 GB Hard Drive Manual

Fujitsu MPB3043AT manual content summary:

  • Fujitsu MPB3043AT | Product Manual - Page 1
    MPB3021AT MPB3032AT MPB3043AT MPB3052AT MPB3064AT DISK DRIVES PRODUCT MANUAL C141-E045-02EN
  • Fujitsu MPB3043AT | Product Manual - Page 2
    Edition 01 02 REVISION RECORD Date published August., 1997 March, 1998 All pages revised. Revised contents Specification No.: C141-E045-**EN The contents of this manual is subject to change without prior notice. All Rights Reserved. Copyright © 1998 FUJITSU LIMITED C141-E045-02EN i
  • Fujitsu MPB3043AT | Product Manual - Page 3
  • Fujitsu MPB3043AT | Product Manual - Page 4
    /MPB3043AT/MPB3052AT/MPB3064AT, a 3.5-inch hard disk drive with a BUILT-IN controller that is compatible with the ATA interface. This manual explains, in detail, how to incorporate the hard disk drives into user systems. This manual assumes that users have a basic knowledge of hard disk drives
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    Conventions for Alert Messages This manual uses the following conventions to show the alert Example) IMPORTANT HA (host adapter) consists of address decoder, driver, and receiver. ATA is an abbreviation of "AT attachment". The disk drive is conformed to the ATA-3 interface The main alert messages in
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    defects that involve adjustment, repair, or replacement. Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside
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  • Fujitsu MPB3043AT | Product Manual - Page 8
    Specifications ...1 - 4 1.2.1 Specifications summary 1 - 4 1.2.2 Model and product number 1 - 5 1.3 Power Requirements...1 - 5 1.4 Environmental Specifications Cable connector specifications 3 - 8 3.3.3 Device connection ...3 - 8 3.3.4 Power supply connector (CN1 3 - 9 3.4 Jumper Settings ...3 -
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    3.4.1 3.4.2 3.4.3 Location of setting jumpers 3 - 9 Factory default setting ...3 - 10 Jumper configuration...3 - 10 CHAPTER 4 THEORY OF DEVICE OPERATION 4 - 1 4.1 Outline...4 - 1 4.2 Subassemblies ...4 - 1 4.2.1 Disk ...4 - 1 4.2.2 Head ...4 - 2 4.2.3 Spindle...4 - 3 4.2.4 Actuator...4 - 3 4.2.5
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    device 5 - 58 5.4.3 Commands without data transfer 5 - 60 5.4.4 Other commands...5 - 61 5.4.5 DMA data transfer commands 5 - 61 5.5 Ultra DMA feature set ...5 - 63 5.5.1 Overview ...5 - 63 5.5.2 Phases of operation...5 - 63 5.5.3 Ultra DMA data in commands 5 - 64 5.5.3.1 Initiating an Ultra DMA
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    Response to the Reset 6 - 1 6.1.1 Response to power-on ...6 - 2 6.1.2 Response to hardware reset 6 - 3 6.1.3 Response to software reset 6 - 4 6.1.4 Response to diagnostic command 6 - 5 6.2 Address Translation...6 - 6 6.2.1 Default parameters...6 - 6 6.2.2 Logical address...6 - 7 6.3 Power Save
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    points 3 - 5 3.6 Service area ...3 - 6 3.7 Connector locations...3 - 7 3.8 Cable connections...3 - 8 3.9 Power supply connector pins (CN1 3 - 9 3.10 Jumper location ...3 - 9 3.11 Factory default setting ...3 - 10 3.12 Jumper setting of master or slave device 3 - 10 3.13 Jumper setting of Cable
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    burst 5 - 89 5.22 Power-on Reset Timing 5 - 90 6.1 Response to power-on ...6 - 2 6.2 Response to hardware reset 6 - 3 6.3 Response to software reset 6 - 4 6.4 Response to diagnostic command 6 - 5 6.5 Address translation (example in CHS mode 6 - 7 6.6 Address translation (example in LBA mode
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    TABLES page 1.1 Specifications ...1 - 4 1.2 Model names and product numbers 1 - 5 1.3 Current and power dissipation 1 - 6 1.4 Environmental specifications 1 - 8 1.5 Acoustic noise specification 1 - 8 1.6 Shock and vibration specification 1 - 9 3.1 Surface temperature measurement points and
  • Fujitsu MPB3043AT | Product Manual - Page 15
  • Fujitsu MPB3043AT | Product Manual - Page 16
    Overview and features are described in this chapter, and specifications and power requirement are described. The MPB3021AT/MPB3032AT/MPB3043AT/MPB3052AT/MPB3064AT are a 3.5-inch hard disk drive with a built-in ATA controller. The disk drive is compact and reliable. 1.1 Features 1.1.1 Functions and
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    can be used over a wide temperature range (5°C to 55°C). (3) Low noise and vibration In Ready status, the noise of the disk drive is only about 3.8 bels (MPB3064AT, Typical Sound Power per ISO7779 and ISO9296). 1.1.3 Interface (1) Connection to interface With the built-in ATA interface controller
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    error recovery. The 18-byte ECC has improved buffer error correction for correctable data errors. (6) Write cache When the disk drive receives a write command, the disk drive posts the command completion at completion of transferring data to the data buffer completion of writing to the disk media
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    ) 20 ms typical Start/Stop time • Start (0 rpm to Drive Read) • Stop (at Power Down) Typical: 8 sec., BIOS specification), formatted capacity, number of cylinders, number of heads, and number of sectors are as follows. Model MPB3021AT MPB3032AT MPB3043AT MPB3052AT MPB3064AT Formatted Capacity
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    product number Table 1.2 lists the model names and product numbers. Model Name MPB3021AT MPB3032AT MPB3043AT MPB3052AT MPB3064AT Table 1.2 Model names and product numbers Capacity (user area) 2162.76 3243.66 4325.52 5249.66 6488.29 Mounting Screw No. 6-32UNC No. 6-32UNC No. 6-32UNC No. 6-32UNC
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    V +5 V MPB 3021AT MPB 3032AT MPB 3043AT MPB 3052AT MPB 3064AT All Models 1300 1500 peak 460 600 peak 115 140 185 460 Typical Power (*2) [ values for +12V and +5V power. *3 Idle mode is in effect when the drive is not reading, writing, seeking, or executing any commands. A portion of the
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    (4) Current fluctuation (Typ.) when power is turned on Note: Maximum current is 1.5 A and is continuance is 1.5 seconds Figure 1.1 Current fluctuation (Typ.) when power is turned on (5) Power on/off sequence The voltage detector circuit monitors +5 V and +12 V. The circuit does not allow a write
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    1.5 Acoustic noise specification Sound Power per ISO7779 and ISO9296 (Typical at 1m) Operating mode Model Idle mode (DRIVE READY) Seek mode (Random) Sound Pressure (Typical at 1m) Idle mode (DRIVE READY) Seek mode (Random) MPB3021AT 3.6 bels 4.2 bels MPB3032AT MPB3043AT 3.7 bels 4.3 bels
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    Table 1.6 lists the shock and vibration specification. Table 1.6 Shock and vibration specification Vibration (swept sine, one octave per specialist maintenance staff member. (3) Service life In situations where management and handling are correct, the disk drive requires no overhaul for five
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    to shipment from the factory (low level format). Thus, the host sees a defect-free device. Alternate sectors are automatically accessed by the disk drive. The user need not be concerned with access to alternate sectors. Chapter 6 describes the low level format at shipping. 1 - 10 C141-E045-02EN
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    CHAPTER 2 DEVICE CONFIGURATION 2.1 Device Configuration 2.2 System Configuration 2.1 Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors
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    . The inner diameter is 25 mm. The number of disks used varies with the model, as described below. The disks are rated at over 40,000 start/stop operations. MPB3021AT: 1 disk MPB3032AT: 2 disks MPB3043AT: 2 disks MPB3052AT: 3 disks MPB3064AT: 3 disks (2) Head The heads are of the contact start/stop
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    Spindle 2 1 0 MMPPBB33005522AT Model Spindle 4 3 2 1 0 Actuator MPB3043AT MMooddeell Spindle 3 2 1 0 Actuator MPB3064AT MMooddeell Spindle 5 4 3 2 1 0 Actuator Actuator Figure 2.2 Configuration of disk media heads (3) Spindle motor The disks are rotated by a direct drive Hall-less DC motor
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    -performance AT controller. 2.2 System Configuration 2.2.1 ATA interface Figures 2.3 and 2.4 show the ATA interface system configuration. The drive has a 40-pin PC AT interface connector and supports the PIO transfer till 16.7 MB/s (ATA-3, Mode 4), the DMA transfer till 16.7 MB/s (ATA-3, Multiword
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    is above configuration, the operation is not guaranteed. Figure 2.4 2 drives configuration IMPORTANT HA (host adapter) consists of address decoder, driver, and receiver. ATA is an abbreviation of "AT attachment". The disk drive is conformed to the ATA-3 interface. At high speed data transfer (PIO
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  • Fujitsu MPB3043AT | Product Manual - Page 32
    CHAPTER 3 INSTALLATION CONDITIONS 3.1 Dimensions 3.2 Mounting 3.3 Cable Connections 3.4 Jumper Settings 3.1 Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm. C141-E045-02EN 3 - 1
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    Figure 3.1 Dimensions 3 - 2 C141-E045-02EN
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    No.6-32UNC screw for the mounting screw and the screw length should satisfy the specification in Figure 3.4. (3) Limitation of side-mounting When the disk drive is mounted using the screw holes on both side of the disk drive, use two screw holes shown in Figure 3.3. Do not use the center hole. For
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    Use these screw holes Do not use this screw holes Figure 3.3 Limitation of side-mounting Bottom surface mounting DE 2 A Frame of system cabinet 2.5 Side surface 2.5 mounting DE 2.5 PCA B Frame of system cabinet 4.5 or less Screw 5.0 or less
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    mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. Pay attention to the air flow to prevent the DE surface temperature from exceeding 60°C. Provide air circulation in the cabinet such that the PCA
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    after installation. - Mounting screw hole [P side] - Cable connection - Mode setting switches [Q side] - Mounting screw hole [R side] - Mounting screw hole Figure 3.6 Service area (6) External magnetic fields Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure
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    connector The disk drive has the connectors and terminals listed below for connecting external devices. Figure 3.7 shows the locations of these connectors and terminals. • Power supply connector (CN1) • ATA interface connector (CN1) Power supply connector (CN1) Mode Setting Pins ATA interface
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    specifications Name Cable socket (closed-end type) Cable socket (through-end type) Signal cable Cable socket housing Contact Signal cable Model Manufacturer FCN-707B040-AU/B Fujitsu FCN-707B040-AU/O Fujitsu cables is not fixed, and so the problem on the crosstalk among signal lines may occur
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    12VDC 2 +12V RETURN 3 +5V RETURN 4 +5VDC Figure 3.9 Power supply connector pins (CN1) 3.4 Jumper Settings 3.4.1 Location of setting jumpers Figure 3.10 shows the location of the jumpers to select drive configuration and functions. CN1 C01 C01 Power supply connector C04 C04 B01 B02 B01/02
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    Master device (device #0) or slave device (device #1) is selected. B02 06 B02 06 B01 05 (a) Master device B01 05 (b) Slave device Figure 3.12 Jumper setting of master or slave device (2) Cable Select (CSEL) In Cable Select mode, the device can be configured either master device or slave device
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    can be done by the special interface cable. Figure 3.13 Jumper setting of Cable Select Figures 3.14 and 3.15 show examples of cable since the slave device is not connected to the CSEL conductor, the CSEL is set to high level. The device is identified as a slave device. CSEL conductor GND
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    (3) Special setting 1 (SP1) The number of cylinders reported by the IDENTIFY DEVICE command is selected. (a) Default mode 2 4 6 2 4 6 2 4 6 1 3 5 Master Device Model MPB3021AT MPB3032AT MPB3043AT MPB3052AT MPB3064AT 1 3 5 Slave Device 1 3 5 Cable Select No. of cylinders 4,470 6,704 8,940 10,
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    . The disk drive has one PCA. For details, see Sections 4.3. 4.2.1 Disk The DE contains the disks with an outer diameter of 95 mm. The MPB3021AT has 1 disk, the MPB3032AT and MPB3043AT have 2 disks. MPB3052AT and MPB3064AT have 3 disks. The head contacts the disk each time the disk rotation stops
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    4.2.2 Head Figure 4.1 shows the read/write head structures. The MPB3021AT has 2 read/write heads, the MPB3032AT has 3, MPB3043AT has 4, MPB3052AT has 5, and MPB3064AT has 6. These heads are raised from the disk surface as the spindle motor approaches the rated rotation speed. MMPPBB33021AMToMdeol
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    makes an air in and out of the DE to prevent unnecessary pressure around the spindle when the disk starts or stops rotating. When disk drives are transported under conditions where the air pressure changes a lot, filtered air is circulated in the DE. The circulation filter cleans out dust and dirt
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    Circuit Configuration Figure 4.2 shows the disk drive circuit configuration. (1) Read/write circuit The reconverted to an analog signal for control of the voice coil motor. (3) Spindle motor driver circuit The circuit measures the interval of a PHASE signal generated by counter-electromotive voltage
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    Figure 4.2 MPB30xxAT Block diagram C141-E045-02EN 4 - 5
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    (data buffer read/write test) after enabling response to the ATA bus. c) After confirming that the spindle motor has reached rated speed, the disk drive releases the heads from the actuator magnet lock mechanism by applying current to the VCM. This unlocks the heads which are parked at the inner
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    buffer write/read test c) Confirming spindle motor speed Release heads from actuator lock d) Initial on-track and read out of system information e) Execute self-calibration f) Drive ready state (command waiting state) End Figure 4.3 Power-on operation sequence C141-E045-02EN 4 - 7
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    the head is positioned. To execute stable fast seek operations, external forces are occasionally sensed. The firmware of the drive measures and stores the force (value of the actuator motor drive current) that balances the torque for stopping head stably. This includes the current offset in the
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    terminates self-calibration and starts executing the command precedingly. In other words, if a disk read or write service is necessary, the disk drive positions the head to the track requested by the host, reads or writes data, and restarts calibration. This enables the host to execute the command
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    or head disconnection. 4.6.2 Write circuit The write data is output from the hard disk controller (HDC) with the NRZ data format, and sent to the PreAMP, and the data is written onto the media. (1) 8/9 GCR The disk drive converts data using the 8/9 (0, 4, 4) group coded recording (GCR) algorithm.
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    Figure 4.4 Read/write circuit block diagram C141-E045-02EN 4 - 11
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    read signal. Cut-off frequency of the low-pass filter and boost-up gain are controlled from each DAC circuit in read channel by an instruction of the serial data signal from MPU (M1). The MPU optimizes the cut-off frequency and boost-up gain according to the transfer frequency of
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    Figure 4.6 PR4 signal transfer C141-E045-02EN 4 - 13
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    data. 4.6.4 Time base generator circuit The drive uses constant density recording to increase total capacity. This is different from the conventional method is set so that the recording density of the inner cylinder of each zone is nearly constant. The drive divides data area into 14 zones to set
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    Table 4.3 Write clock frequency and transfer rate of each zone Zone Cylinder Transfer rate [MB/s] 0 1 2 3 4 5 6 7 0 661 1198 1939 2673 3333 3959 4748 to to to to to to to to 660 1197 1938 2672 3332 3958 4747 5216 16.71 16.35 15.82 15.18 14.68 14.15 13.44 13.06 Zone Cylinder
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    Current Sense Resistor VCM: Voice Coil Motor (6) Spindle motor control (7) Driver Spindle motor Figure 4.7 Block diagram of servo control circuit (1) Microprocessor speed when power is applied. b. Move head to reference cylinder Drives the VCM to position the head at the any cylinder in the
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    c. Seek to specified cylinder Drives the VCM to position the head to the specified cylinder. d. Calibration Senses and stores the thermal offset between heads and the mechanical forces on the
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    . (4) D/A converter (DAC) The D/A converter (DAC) converts the VCM drive current value (digital value) calculated by the DSP unit into analog values and motor coil according to the differentiation (aberration). (7) Driver circuit The driver circuit is a power amplitude circuit that receives signals
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    rotational speed of the spindle can be controlled on this cylinder area for head moving. 4.7.3 Servo frame format As the servo information, the drive uses the two-phase servo generated from the gray code and servo A to D. This servo information is used for positioning operation of radius direction
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    surface. The MPU fetches the position sense data on the servo frame at a constant interval of sampling time, executes calculation, and updates the VCM drive current. The servo control of the actuator includes the operation to move the head to the reference cylinder, the seek operation to move the
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    access to the disk. If a read or instruction is issued, the MPU seeks the desired track. drive current by setting the calculated result into the D/A converter. The calculation is digitally executed by the firmware driver (called SVC hereafter). The firmware operates on the MPU manufactured by Fujitsu
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    e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a specific period, the MPU resets the SVC and starts from the beginning. When a PHASE signal is sent, the SVC enters the acceleration mode. (2) Acceleration mode In
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    CHAPTER 5 INTERFACE 5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands 5.4 Command Protocol 5.5 Ultra DMA feature Set 5.6 Timing C141-E045-02EN 5 - 1
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    5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals. Host DD(15:0) DATA BUS IDD DMACK-: DMA ACKNOWLEDGE DMARQ: DMA REQUEST DIOW-: I/O WRITE DIOR- : I/O READ INTRQ : INTERRUPT REQUEST IOCS16-: IOCS 16 PDIAG- : PASSED DIAGNOSTIC IORDY : I/O CHANNEL READY DASP- :
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    5.1.2 Signal assignment on the connector Table 5.1 shows the signal assignment on the interface connector. Table 5.1 Signal assignment on the interface connector Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Signal RESET- DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND DMARQ
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    [signal] DIOR-, HDMARDY-, HSTROBE INTRQ IOCS16- CS0- CS1- DA 0-2 KEY PIDAG- DASP- [I/O] [Description] I DIOR- is the strobe signal asserted by the host to read device registers or the data port. HDMARDY- is a flow control signal for Ultra DMA data in bursts. This signal is asserted by the host to
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    [signal] IORDY, DDMARDY-, DSTROBE CSEL DMACK- DMARQ GND [I/O] [Description] O This signal is negated to extend the host transfer cycle of any host register access (Read or Write) when the device is not ready to respond to a data transfer request. DDMARDY- is a flow control signal for Ultra DMA
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    cylinderhead-sector (CHS) or Logical block address (LBA) mode. The IDENTIFY DEVICE information indicates whether the device supports the LBA mode. When the host system specifies the LBA mode by setting bit 6 in the Device/Head register to 1, HS3 to HS0 bits of the Device/Head register indicates the
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    registers for read or write operation other than the Data registers can be accessed by 8 bit data bus (DATA0 to DATA7). 3. When reading the Drive Address register, bit 7 is high-impedance state. 4. The LBA mode is specified, the Device/Head, Cylinder High, Cylinder Low, and Sector Number registers
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    5.2.2 Command block registers (1) Data register (X'1F0') The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or LBA mode. (2) Error register (X'1F1') The Error register indicates the status of the command executed by the
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    , the diagnostic code of the slave device is posted. (3) Features register (X'1F1') The Features register provides specific feature to a command. For instance, it is used with SET FEATURES command to enable or disable caching. (4) Sector Count register (X'1F2') The Sector Count register indicates
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    the end of a command, the contents of this register are updated to the current cylinder number. The high-order 8 bits of the cylinder address are set to the Cylinder High register. Under the LBA mode, this register indicates LBA bits 23 to 16. (8) Device/Head register (X'1F6') The contents of this
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    BSY Bit 6 DRDY Bit 5 DF Bit 4 DSC Bit 3 DRQ Bit 2 0 Bit 1 0 Bit 0 ERR - Bit 7: - Bit 6: - Bit 5: - Bit 4: Busy (BSY) bit. This bit is set whenever the Command register is accessed. Then this bit is cleared when the command is completed. However, even if a command is being executed, this bit
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    - Bit 3: - Bit 2: - Bit 1: - Bit 0: Data Request (DRQ) bit. This bit indicates that the device is ready to transfer data of word unit or byte unit between the host system and the device. Always 0. Always 0. Error (ERR) bit. This bit indicates that an error was detected while the previous command
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    Bit 4 X Bit 3 X Bit 2 SRST Bit 1 nIEN Bit 0 0 - Bit 2: - Bit 1: SRST is the host software reset bit. When this bit is set, the device is held reset state. When two device are daisy chained on the interface, setting this bit resets both device simultaneously. The slave device is not required to
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    5.3.1 Command code and parameters Table 5.3 lists the supported commands, command code and the registers that needed parameters are RECALIBRATE SEEK INITIALIZE DEVICE DIAGNOSTIC IDENTIFY DEVICE IDENTIFY DEVICE DMA SET FEATURES SET MULTIPLE MODE EXECUTE DEVICE DIAGNOSTIC FORMAT TRACK READ LONG WRITE
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    Count Register SN : Sector Number Register CY: Cylinder Registers DH : Drive/Head Register R: Retry at error 1 = Without retry 0 = with retry Y: Necessary to set parameters Y*: Necessary to set parameters under the LBA mode. N: Necessary to set parameters (The parameter is ignored if it is
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    of the I/O registers at command completion are shown as following in this subsection. Example: READ SECTOR(S) WITH RETRY At command issuance (I/O registers setting contents) Bit 76543210 1F7H(CM) 1F6H(DH) 00100000 × L × DV Head No. / LBA [MSB] 1F5H(CH) 1F4H(CL) Start cylinder address [MSB
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    seek. After the head reaches to the specified track, the device reads the target sector. The DRQ bit of the Status register is always set prior to the data transfer regardless of an error condition. Upon the completion of the command execution, command block registers contain the cylinder, head
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    signal) on each every sector. An interrupt is generated after the transfer of a block of sectors for which the number is specified by the SET MULTIPLE MODE command. The implementation of the READ MULTIPLE command is identical to that of the READ SECTOR(S) command except that the number of sectors
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    1 2 3 4 Block Status read Status read 5 6 7 8 Block 9 Partial block Figure 5.2 Execution example of READ MULTIPLE command At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 0 0 0 1 0 0 1F6H(DH) × L × DV Start head No. /LBA [MSB] 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC
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    Note: If the command is terminated due to an error, the remaining number of sectors for which data was not transferred is set in this register. (3) READ DMA (X'C8' or X'C9') This command operates similarly to the READ SECTOR(S) command except for following events. • The data transfer starts
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    00 (*1) Error information *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. (4) READ VERIFY SECTOR(S) (X'40' or X'41') This command operates similarly to the READ SECTOR(S) command except that the data is
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    00 (*1) Error information *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. (5) WRITE SECTOR(S) (X'30' or X'31') This command writes data of sectors from the address specified in the Device/Head, Cylinder
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    INTRQ) signal) on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE MODE command. The implementation of the WRITE MULTIPLE command is identical to that of the WRITE SECTOR(S) command except that the number of sectors
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    sector are undefined. To obtain a valid error information, the host should retry data transfer as an individual requests. At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 0 0 0 1 0 1 1F6H(DH) × L × DV Start head No. /LBA [MSB] 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR
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    (*1) Error information *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. (8) WRITE VERIFY (X'3C') This command operates similarly to the WRITE SECTOR(S) command except that the device verifies each sector
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    Status register, clears the BSY bit, and generates an interrupt. This command can be issued in the LBA mode. At command issuance (I/O registers setting contents) 1F7H(CM) 0 0 0 1 x x x x 1F6H(DH) × × × DV xx 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(FR) xx 5 - 26
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    registers. After completing the seek operation, the device clears the BSY bit in the Status register and generates an interrupt. The IDD always sets the DSC bit (Drive Seek Complete status) of the Status register to 1. In the LBA mode, this command performs the seek operation to the cylinder and
  • Fujitsu MPB3043AT | Product Manual - Page 93
    setting of disabling the reverting to default setting. In LBA mode The device ignores the L bit specification and operates with the CHS mode specification command, the drive sets the BSY bit of Status register and sets required parameter information in the sector buffer. The device then sets the DRQ
  • Fujitsu MPB3043AT | Product Manual - Page 94
    At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 0 1 1 0 0 1F6H(DH) × × × DV xx 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(FR) xx At command completion (I/O
  • Fujitsu MPB3043AT | Product Manual - Page 95
    set by READ/WRITE MULTIPLE command Total number of user addressable sectors (LBA mode only) MPB3021AT: X'00407496' MPB3032AT: X'0060AB30' MPB3043AT: X'0080E92C' MPB3052AT: X'009C73C2' MPB3064AT: X'00C15DC2' Retired Multiword DMA transfer mode *9 Advance PIO transfer mode support status
  • Fujitsu MPB3043AT | Product Manual - Page 96
    blank code (X'20') One of following model numbers; MPB3021AT, MPB3032AT, MPB3043AT, MPB3052AT, MPB3064AT *5 Word 49: Capabilities Bit 15-14: Reserved Bit 13: Standby timer value 0 = vendor specific Bit 12: Reserved Bit 11: IORDY support 1=Supported Bit 10: IORDY inhibition 0=Disable inhibition
  • Fujitsu MPB3043AT | Product Manual - Page 97
    Supported=1 Bit 2: ATA-2 Supported=1 Bit 1: ATA-1 Supported=1 Bit 0: Undefined *12 Word 82: Support of command sets Bit 15-4: Reserved Bit 3: Power Management feature set supported=1 Bit 2: Removable feature set supported=0 Bit 1: Security feature set supported=0 Bit 0: SMART feature set supported
  • Fujitsu MPB3043AT | Product Manual - Page 98
    the device clears the BSY bit, and generates an interrupt. If the value in the Features register is not supported or it is invalid, the device posts an ABORTED COMMAND error. Table 5.5 lists the available values and operational modes that may be set in the Features register. C141-E045-02EN 5 - 33
  • Fujitsu MPB3043AT | Product Manual - Page 99
    . X'03' Specifies the transfer mode. Supports PIO mode 4, single word DMA mode 2, and multiword DMA mode regardless of Sector Count register contents. X'55' Disables read cache function. X'66' Disables the reverting to power-on default settings after software reset. X'82' Disables the write
  • Fujitsu MPB3043AT | Product Manual - Page 100
    the IDD can operate with the PIO transfer mode 4 and multiword DMA transfer mode 2 regardless of reception of the SET FEATURES command for transfer mode setting. The IDD supports following values in the Sector Count register value. If other value than below is specified, an ABORTED COMMAND error is
  • Fujitsu MPB3043AT | Product Manual - Page 101
    hardware reset, the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the default mode. Regarding software reset, the mode set prior to software reset is retained after software reset. The parameters for the multiple commands which are posted to the host system when the IDENTIFY
  • Fujitsu MPB3043AT | Product Manual - Page 102
    (16) EXECUTE DEVICE DIAGNOSTIC (X'90') This command performs an internal diagnostic test (self-diagnosis) of the device. This command usually sets the DRV bit of the Drive/Head register is to 0 (however, the DV bit is not checked). If two devices are present, both devices execute self-diagnosis. If
  • Fujitsu MPB3043AT | Product Manual - Page 103
    (17) FORMAT TRACK (X'50') Upon receipt of this command, the device sets the DRQ bit and waits the completion of 512byte format parameter transfer from the BSY bit and generates an interrupt. The drive supports this command for keep the compatibility with previous drive only. (18) READ LONG (X'22'
  • Fujitsu MPB3043AT | Product Manual - Page 104
    does not generate ECC bytes by itself. The WRITE LONG command supports only single sector operation. The number of ECC bytes to be transferred is fixed to 4 bytes and can not be changed by the SET FEATURES command. This command is operated under the following conditions: • The command
  • Fujitsu MPB3043AT | Product Manual - Page 105
    bit, and generates an interrupt. After that, the host system can read up to 512 bytes of data from the buffer. At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 1 0 1 0 0 1F6H(DH) × × × DV xx 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(FR) xx 5 - 40
  • Fujitsu MPB3043AT | Product Manual - Page 106
    is transferred from the host and the device writes the data to the sector buffer, then generates an interrupt. At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 1 1 0 0 0 1F6H(DH) × × × DV xx 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(FR) xx At
  • Fujitsu MPB3043AT | Product Manual - Page 107
    Point of timer Disable of timer 15 seconds (Value ×5) seconds (Value - 240) ×30 minutes 21 minutes 8 hours 21 minutes 15 seconds At command issuance (I/O registers setting contents) 1F7H(CM) X'97' or X'E3' 1F6H(DH) × × × DV xx 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) xx xx xx Period of
  • Fujitsu MPB3043AT | Product Manual - Page 108
    enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. This command does not support the automatic power-down function. At command issuance (I/O registers setting contents) 1F7H(CM) X'95' or X'E1' 1F6H(DH) × × × DV xx 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx
  • Fujitsu MPB3043AT | Product Manual - Page 109
    command, the device sets the BSY bit received, the device processes the command after driving the spindle motor. At command issuance (I/O registers setting contents) 1F7H(CM) X'96' or or X'E0') Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby
  • Fujitsu MPB3043AT | Product Manual - Page 110
    All I/O register outputs are in high-impedance state. The only way to release the device from sleep mode is to execute a software or hardware reset. At command issuance (I/O registers setting contents) 1F7H(CM) X'99' or X'E6' 1F6H(DH) × × × DV xx 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H
  • Fujitsu MPB3043AT | Product Manual - Page 111
    host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector registers. The device sets the BSY bit and sets the following register value. After that, the device clears the BSY bit and generates an interrupt. Power save mode • During moving to
  • Fujitsu MPB3043AT | Product Manual - Page 112
    failure predictions according to a subcommand specified in the FR register. If the value specified in the FR register is supported, the Aborted Command error is posted. It is necessary for the host to set the keys (CL = 4Fh and CH = C2h) in the CL and CH registers prior to issuing this command
  • Fujitsu MPB3043AT | Product Manual - Page 113
    SMART Disable Operations: This subcommand disables the failure prediction feature. The setting is maintained even when the device is turned off and then on. 4Fh and C2h are loaded into the CL and CH registers. After the settings for the CL and CH registers have been determined, the device clears the
  • Fujitsu MPB3043AT | Product Manual - Page 114
    nearing the end of it life . In this case, the host recommends that the user quickly backs up the data. At command issuance (I-O registers setting contents) 1F7H(CM) 1 0 1 1 0 0 0 0 1F6H(DH) × × × DV xx 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) Key (C2h) Key (4Fh) xx xx Subcommand
  • Fujitsu MPB3043AT | Product Manual - Page 115
    attribute 30 that of bytes 02 to 0D.) 169 16A Reserved to 16F 170 Failure prediction capability flag 171 172 Reserved to 181 182 Vendor specific to 1FE 1FF Check sum 5 - 50 C141-E045-02EN
  • Fujitsu MPB3043AT | Product Manual - Page 116
    Table 5.9 Format of insurance failure threshold value data Byte Item 00 Data format version number 01 02 Attribute 1 Attribute ID 03 Insurance failure threshold 04 Threshold 1 (Threshold of Reserved attribute 1) to 0D 0E Threshold 2 to (The format of each threshold value is the same
  • Fujitsu MPB3043AT | Product Manual - Page 117
    • Attribute ID The attribute ID is defined as follows: Attribute ID Attribute name 0 (Indicates unused attribute data.) 1 Read error rate 2 Throughput performance 3 Spin up time 4 Number of times the spindle motor is activated 5 Number of alternative sectors 7 Seek error rate 8
  • Fujitsu MPB3043AT | Product Manual - Page 118
    device automatically saves the attribute value data to a medium after the previously set operation. Bits 2 to 15: Reserved bits • Check sum Two's complement at a time from the beginning. • Insurance failure threshold The limit of a varying attribute value. The host compares the attribute values with
  • Fujitsu MPB3043AT | Product Manual - Page 119
    to be flushed and the success of the operation. NOTE - This command may take longer than 30 s to complete. If the command is not supported, the device shall set the ABRT bit to one. An unrecoverable error encountered during execution of writing data results in the termination of the command and the
  • Fujitsu MPB3043AT | Product Manual - Page 120
    V V V V SEEK V V V V V INITIALIZE DEVICE PARAMETERS V V V V IDENTIFY DEVICE V V V V IDENTIFY DEVICE DMA V V V V SET FEATURES V V V V SET MULTIPLE MODE V V V V EXECUTE DEVICE DIAGNOSTIC * * * * * V FORMAT TRACK V V V V V READ LONG V V V V V WRITE
  • Fujitsu MPB3043AT | Product Manual - Page 121
    and prepares for data transfer. d) When one sector (or block) of data is available for transfer to the host, the device sets DRQ bit and clears BSY bit. The drive then asserts INTRQ signal. e) After detecting the INTRQ signal assertion, the host reads the Status register. The host reads one sector
  • Fujitsu MPB3043AT | Product Manual - Page 122
    data from the buffer without reading from the disk medium. Figure 5.3 Read Sector(s) command protocol Even if the error status exists, the drive makes a preparation (setting the DRQ bit) of data transfer. It is up to the host whether data is transferred. In other words, the host should receive
  • Fujitsu MPB3043AT | Product Manual - Page 123
    INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 50 µs after the completion of the sector data transfer. Note that a command code in the Command register. The drive sets the BSY bit of the Status register. 5 - 58 C141-E045-02EN
  • Fujitsu MPB3043AT | Product Manual - Page 124
    transferring the data of the sector, the device clears BSY bit and asserts INTRQ signal. If transfer of another sector is requested, the drive sets the DRQ bit. g) After detecting the INTRQ signal assertion, the host reads the Status register. h) The device resets INTRQ (the interrupt signal). I) If
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    condition, normal data transfer operation is not assured guaranteed. When the host issues the command even if the drive requests the data transfer (DRQ bit is set), or when the host executes resetting, the device correct operation is not guaranteed. 5.4.3 Commands without data transfer Execution
  • Fujitsu MPB3043AT | Product Manual - Page 126
    , Cylinder, and Device/Head register. b) The host initializes the DMA channel c) The host writes a command code in the Command register. d) The device sets the BSY bit of the Status register. e) The device asserts the DMARQ signal after completing the preparation of data transfer. The device asserts
  • Fujitsu MPB3043AT | Product Manual - Page 127
    Parameter write ~ Command BSY • • DRDY INTRQ • • DRQ Data transfer • • Status read Expanded [Single Word DMA transfer] DRQ DMARQ DMACK- IOR- or IOW- Word 0 1 2 [Multiword DMA transfer] DRQ DMARQ DMACK- IOR- or IOW- Word 0 1 n-1 Figure 5.7 Normal DMA data transfer
  • Fujitsu MPB3043AT | Product Manual - Page 128
    an Ultra DMA burst a sender shall always drive data onto the bus, and after a sufficient that the frequency of STROBE is limited to the same frequency as the data support of the Ultra DMA feature and the Ultra DMA Modes the device is capable of supporting. The Set transfer mode subcommand in the SET
  • Fujitsu MPB3043AT | Product Manual - Page 129
    the detailed protocol descriptions for each of these phases, 5.6.4 defines the specific timing requirements). In the following rules DMARDY- is used in cases that the first data word has been received). 10) The device shall drive DD (15:0) no sooner than tZAD after the host has asserted DMACK-, negated
  • Fujitsu MPB3043AT | Product Manual - Page 130
    DD (15:0). 5.5.3.2 The data in transfer The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.3 and 5.6.4.2): 1) The device shall drive a data word onto DD (15:0). 2) The device shall generate a DSTROBE edge to latch the new word no sooner than
  • Fujitsu MPB3043AT | Product Manual - Page 131
    order they are listed unless otherwise specifically allowed (see 5.6.4.5 and 5.6.4.2 for specific timing requirements): 1) The device shall has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (6), the host shall place the result of its CRC calculation
  • Fujitsu MPB3043AT | Product Manual - Page 132
    occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.6 and 5.6.4.2 for specific timing requirements): 1) The host shall not initiate later than tAZ after negating DMARQ. 9) The host shall drive DD (15:0) no sooner than tZAH after the device has negated DMARQ. For this
  • Fujitsu MPB3043AT | Product Manual - Page 133
    placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (9), the host shall place the result of its occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.7 and 5.6.4.2 for specific timing requirements): 1) The host shall keep DMACK-
  • Fujitsu MPB3043AT | Product Manual - Page 134
    The data out transfer The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.8 and 5.6.4.2 for specific timing requirements): 1) The host shall drive a data word onto DD (15:0). 2) The host shall generate an HSTROBE edge to latch the new word
  • Fujitsu MPB3043AT | Product Manual - Page 135
    an Ultra DMA data out burst The following stops shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.10 and 5.6.4.2 for specific timing requirements): 1) The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges. 2) The host
  • Fujitsu MPB3043AT | Product Manual - Page 136
    terminating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.11 and 5.6.4.2 for specific timing requirements): 1) The device shall not initiate Ultra DMA burst termination until at least one data word of an
  • Fujitsu MPB3043AT | Product Manual - Page 137
    device shall report the first error that occurred. g) For READ DMA or WRITE DMA commands: When a CRC error is detected, it shall be reported by setting both ICRC and ABRT (bit 7 and bit 2 in the Error register) to one. ICRC is defined as the "Interface CRC Error" bit. The host shall
  • Fujitsu MPB3043AT | Product Manual - Page 138
    I) The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1. Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the
  • Fujitsu MPB3043AT | Product Manual - Page 139
    5.6 Timing 5.6.1 PIO data transfer Figure 5.9 shows of the data transfer timing between the device and the host system. 5 - 74 C141-E045-02EN
  • Fujitsu MPB3043AT | Product Manual - Page 140
    t0 Addresses DIOR-/DIOW- Write data DD0-DD15 t1 t2 t9 t2i t3 t4 Read data DD0-DD15 IOCS16- IORDY t7 t10 t5 t6 t11 t12 Symbol Timing parameter t0 Cycle time t1 Data register selection setup time for DIOR-/DIOW- t2 Pulse width of DIOR-/DIOW- t2i Recovery time of DIOR-/DIOW- t3 Data
  • Fujitsu MPB3043AT | Product Manual - Page 141
    5.6.2 Single word DMA data transfer Figure 5.10 show the single word DMA data transfer timing between the device and the host system. DMARQ DMACK- DIOR-/DIOW- t0 tC tI tJ tD Write data DD0-DD15 tG tH Read data DD0-DD15 tE tF Symbol Timing parameter t0 Cycle time tC Delay time from
  • Fujitsu MPB3043AT | Product Manual - Page 142
    5.6.3 Multiword data transfer Figure 5.11 shows the multiword DMA data transfer timing between the device and the host system. DMARQ DMACK- DIOR-/DIOW- t0 tC tJ tI tD tK Write data DD0-DD15 tG tH Read data DD0-DD15 tE tF Symbol Timing parameter t0 Cycle time tC Delay time from DMACK
  • Fujitsu MPB3043AT | Product Manual - Page 143
    5.6.4 Ultra DMA data transfer Figures 5.12 through 5.21 define the timings associated with all phases of Ultra DMA bursts. Table 5.12 contains the values for the timings for each of the Ultra DMA Modes. 5.6.4.1 Initiating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for
  • Fujitsu MPB3043AT | Product Manual - Page 144
    to first negate DSTROBE from STOP during a data in burst) 0 150 Limited interlock time (see Note 1) 20 Interlock time with minimum (see Note Maximum time allowed for output drivers to release (from being asserted or nMeignaitmedu)m delay time required for output 20 drivers to assert or negate
  • Fujitsu MPB3043AT | Product Manual - Page 145
    to be released tZIORDY 0 0 0 Minimum time device shall wait before driving IORDY tACK 20 20 20 Setup and hold times for DMACK- (before assertion has no maximum time value. tMLI is a limited time-out that has a defined minimum. tLI is a limited time-out, that has a defined maximum. 2)
  • Fujitsu MPB3043AT | Product Manual - Page 146
    for each of the Ultra DMA Modes. Note: DD (15:0) and DSTROBE are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they
  • Fujitsu MPB3043AT | Product Manual - Page 147
    5.6.4.4 Host pausing an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: 1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY- is negated. 2) If the tSR timing is not satisfied, the host
  • Fujitsu MPB3043AT | Product Manual - Page 148
    5.6.4.5 Device terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.15 Device terminating an Ultra
  • Fujitsu MPB3043AT | Product Manual - Page 149
    5.6.4.6 Host terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.16 Host terminating an Ultra DMA
  • Fujitsu MPB3043AT | Product Manual - Page 150
    5.6.4.7 Initiating an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. Figure 5.17 Initiating an Ultra DMA data out burst
  • Fujitsu MPB3043AT | Product Manual - Page 151
    each of the Ultra DMA Modes. Note: DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they
  • Fujitsu MPB3043AT | Product Manual - Page 152
    5.6.4.9 Device pausing an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: 1) The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY- is negated. 2) If the tSR timing is not satisfied,
  • Fujitsu MPB3043AT | Product Manual - Page 153
    5.6.4.10 Host terminating an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.20 Host terminating an Ultra
  • Fujitsu MPB3043AT | Product Manual - Page 154
    5.6.4.11 Device terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.21 Device terminating an
  • Fujitsu MPB3043AT | Product Manual - Page 155
    RESET-), and Software Reset. (2) Master and slave devices are present (2-drives configuration) [Master device] BSY DASP- [Slave device] BSY PDIAG- DASP- Clear Reset tN tP tR tQ tS Symbol Timing parameter tM Pulse width of RESET- tN Time from RESET- negation to BSY set
  • Fujitsu MPB3043AT | Product Manual - Page 156
    CHAPTER 6 OPERATIONS 6.1 Device Response to the Reset 6.2 Address Translation 6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead Cache 6.6 Write Cache 6.1 Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD
  • Fujitsu MPB3043AT | Product Manual - Page 157
    6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for up to 450 ms to confirm presence of a slave device (device 1). The master device recognizes presence of the slave device when it confirms assertion of
  • Fujitsu MPB3043AT | Product Manual - Page 158
    6.1.2 Response to hardware reset Response to RESET- (hardware reset through the interface) is similar to the power-on reset. Upon receipt of hardware reset, the master device checks a DASP- signal for up to 450 ms to confirm presence of a slave device. The master device recognizes the presence of
  • Fujitsu MPB3043AT | Product Manual - Page 159
    completed the self-diagnosis successfully. After the slave device receives the software reset, the slave device shall report its presence and the result of : negated within 1 ms and asserted within 30 seconds When the IDD is set to a slave device, the IDD asserts the DASP- signal when negating the
  • Fujitsu MPB3043AT | Product Manual - Page 160
    of the self-diagnostics to the master device as described below: PDIAG- signal: negated within 1 ms and asserted within 5 seconds When the IDD is set to a slave device, the IDD asserts the DASP- signal when negating the PDIAG- signal, and negates the DASP- signal when asserting the PDIAG- signal
  • Fujitsu MPB3043AT | Product Manual - Page 161
    This is called as the default translation mode. The parameters in Table 6.1 are called BIOS specification. Table 6.1 Default parameters Number of cylinders Parameters (logical) Number of head Number of sectors/track Formatted capacity (MB) MPB 3064AT 13,410 15 63 6,488.2 MPB 3052AT 10,850 5,249
  • Fujitsu MPB3043AT | Product Manual - Page 162
    head 0 LH4 15 16 LS 63 LS1 78 79 LS 63 LS1 LS2 LH5 LH6 ex: Zone 0 Physical parameter - Physical sector: 1 to 300 Specification of INITIALIZE DEVICE PARAMETERS command - Logical head: LH = 0 to 14 - Logical sector: LS = 1 to 63 Figure 6.5 Address translation (example in CHS mode) C141
  • Fujitsu MPB3043AT | Product Manual - Page 163
    supplying to the part of the circuit is turned off. There are three types of power save modes: • Idle mode • Standby mode • Sleep mode The drive moves from the Active mode to the idle mode by itself. 6 - 8 C141-E045-02EN
  • Fujitsu MPB3043AT | Product Manual - Page 164
    commands is issued. • Reset (hardware or software) (2) Idle mode In this mode, circuits on the device is set to power save mode. The device enters because the access to the disk medium cannot be made immediately. The drive enters the standby mode under the following conditions: • A STANDBY or
  • Fujitsu MPB3043AT | Product Manual - Page 165
    enters only the standby mode from the sleep mode. The only method to return from the standby mode is to execute a software or hardware reset. The drive enters the sleep mode under the following condition: • A SLEEP command is issued. Issued commands are invalid (ignored) in this mode. 6.3.2 Power
  • Fujitsu MPB3043AT | Product Manual - Page 166
    6.4.1 Spare area Following two types of spare area are provided for every physical head. 1) Spare cylinder for sector slip: used for alternating defective sectors at formatting in shipment (11 cylinders/head) 2) Spare cylinder for alternative assignment: used for alternative assignment by automatic
  • Fujitsu MPB3043AT | Product Manual - Page 167
    (2) Alternate cylinder assignment A defective sector is assigned to the spare sector in the alternate cylinder. This processing is performed when the automatic alternate processing is performed. Figure 6.8 shows an example where (physical) sector 5 is detective on head 0 in cylinder 0. Index
  • Fujitsu MPB3043AT | Product Manual - Page 168
    can be transferred from the data buffer without accessing the disk medium. The host can thus access data at higher speed. 6.5.1 Data buffer configuration The drive has a 256-KB data buffer. The buffer is used by divided into three parts; for read commands, for write commands, and for MPU work (see
  • Fujitsu MPB3043AT | Product Manual - Page 169
    READ MULTIPLE • READ DMA When caching operation is disabled by the SET FEATURES command, no caching operation is performed. (2) Data that are is performed to the data buffer for read command priority, caching write data is limited to the case that the hit check is missed at the data buffer for read
  • Fujitsu MPB3043AT | Product Manual - Page 170
    3) Caching operation is inhibited by the SET FEATURES command. 4) Issued command is terminated with an error. 5) Soft reset or hard reset occurs, or power is turned off of previous read command. When it is not sequential, the drive checks that the sequential read command is executed for last received
  • Fujitsu MPB3043AT | Product Manual - Page 171
    1) Sets the host address pointer (HAP) and the disk address pointer (DAP) to the requested data and transferring the requested data to the host system had been completed, the disk drive stops command execution without performing the readahead operation. HAP (stopped) Read-requested data (stopped)
  • Fujitsu MPB3043AT | Product Manual - Page 172
    command is a sequential command and performs the read-ahead operation after reading the requested data. 1) At receiving the sequential read command, the disk drive sets the DAP and HAP to the sequential address of the last read command and reads the requested data. HAP Mis-hit data Empty data DAP
  • Fujitsu MPB3043AT | Product Manual - Page 173
    read-ahead operation of the new continuous data to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring data to the host system. 1) In the case that the contents of buffer is as follows at receiving a read command; HAP (Completion of
  • Fujitsu MPB3043AT | Product Manual - Page 174
    to item (1)). Processing is the same as item a. above (3) Full hit (hit all) All requested data are stored in the data buffer. The disk drive starts transferring the requested data from the address of which the requested data is stored. After completion of command, a previously existed cache data
  • Fujitsu MPB3043AT | Product Manual - Page 175
    is as follows for example and the previous command is a sequential read command, the disk drive sets the HAP to the address of which the hit data is stored. Last position at previous read command HAP HAP (set to hit position for data transfer) Cache data Full hit data Cache data DAP Last
  • Fujitsu MPB3043AT | Product Manual - Page 176
    is stored, and sets the DAP to the address just after the partially hit data. HAP Partially hit data Lack data DAP 2) The disk drive starts transferring partially from the disk media at the same time. However, the disk drive does not perform the read-ahead operation newly. Requested data to be
  • Fujitsu MPB3043AT | Product Manual - Page 177
    soft reset is received or the write cache function is disabled by the SET FEATURES command during unwritten data is kept, the instruction is not executed until remaining unwritten data is written onto the disk medium. The drive uses a write data as a read cache data. When a read command is issued to
  • Fujitsu MPB3043AT | Product Manual - Page 178
    The releasing the disable state can be done by the SET FEATURES command. When the power of the drive is turned on after the power is turned off once, the occurred error is for which command generally. Therefore, it is very hard to retry the unrecoverable write error for the host in the write cache
  • Fujitsu MPB3043AT | Product Manual - Page 179
    Comments concerning this manual can be directed to one of the following addresses: FUJITSU LIMITED Business Planning Solid Square East Tower 580 Horikawa-cho,Saiwai-ku, Kawasaki, 210-0913, Japan TEL: 81-44-540-4056 FAX: 81-44-540-4123 FUJITSU COMPUTER PRODUCTS OF AMERICA, INC. 2904
  • Fujitsu MPB3043AT | Product Manual - Page 180
    FUJITSU LIMITED Reader Comment Form Publication No. We would appreciate your comments and Very Good Fair Good Poor Very Poor Your other comments may be entered here. Please be specific and give page, paragraph and line number references where applicable. Well Organized Clean Your Name &
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C141-E045-02EN
MPB3021AT
MPB3032AT
MPB3043AT
MPB3052AT
MPB3064AT
DISK DRIVES
PRODUCT MANUAL