HP ProLiant SL165s Memory technology evolution: an overview of system memory t
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- HP ProLiant SL165s | Memory technology evolution: an overview of system memory t - Page 1
DDR-3 ...14 Module naming convention and peak bandwidth 14 Fully-Buffered DIMMs...15 FB-DIMM architecture...16 Challenges ...17 Rambus DRAM ...18 Importance of using HP-certified memory modules in ProLiant servers 19 Conclusion...19 For more information...20 Call to action ...20 - HP ProLiant SL165s | Memory technology evolution: an overview of system memory t - Page 2
in ProLiant servers. HP is committed to providing customers with the most reliable memory at the lowest possible cost. This paper main memory. Cache memory consists of very fast static RAM (SRAM) and is usually integrated with the processor. Main memory consists of DRAM chips that can be packaged in - HP ProLiant SL165s | Memory technology evolution: an overview of system memory t - Page 3
/command bus is a set of traces that carry signals identifying the location of data in memory. The command portion of the address/command bus conveys instructions such as read, write, or refresh. When FPM or EDO memory writes data to a particular cell, the location where the data will be written is - HP ProLiant SL165s | Memory technology evolution: an overview of system memory t - Page 4
DRAM. For synchronous DRAM, the time is converted to number of memory bus clocks. Chipsets and system bus timing All computer components that execute instructions or transfer data are controlled by a system bus clock. The system chipset controls the speed, or frequency, of the system bus clock and - HP ProLiant SL165s | Memory technology evolution: an overview of system memory t - Page 5
more than others have. For this reason, the components in a typical server are controlled by different clocks that run at different, but related, speeds must wait one or more additional clock cycles for data or instructions due to clock resynchronization. In contrast, synchronized components know on - HP ProLiant SL165s | Memory technology evolution: an overview of system memory t - Page 6
with every clock cycle after the first access (6-1-1-1) before the memory controller has to send another CAS. Figure 4. Burst mode access. NOP is a "No Operation" instruction. Clock Command Address Data Active NOP NOP Read NOP NOP NOP NOP NOP NOP Row Col Data Data Data Data 64b 64b 64b 64b - HP ProLiant SL165s | Memory technology evolution: an overview of system memory t - Page 7
must take a break (be refreshed), breaks are staggered so that at least one assistant is working at all times. Therefore, they retrieve the data much faster than a single assistant could get the same data from one whole page, especially since no data can be accessed when a single assistant takes - HP ProLiant SL165s | Memory technology evolution: an overview of system memory t - Page 8
DIMM Configurations Single-sided and double-sided DIMMs Each DRAM chip on a DIMM provides either 4 bits or 8 bits of a 64-bit data word. Chips that provide 4 bits are called x4 (by 4), and chips that provide 8 bits are called x8 (by 8). It takes eight x8 chips or sixteen x4 chips to make a 64-bit - HP ProLiant SL165s | Memory technology evolution: an overview of system memory t - Page 9
integrity. support, the server HP-certified memory modules in ProLiant servers" section). Another important difference between single-rank and dual-rank DIMMs is cost. Typically, memory costs increase with DRAM density. For example, the cost of an advanced, high-density DRAM chip is typically much - HP ProLiant SL165s | Memory technology evolution: an overview of system memory t - Page 10
independently of each other to access up to two DIMMs per channel. This enables a process called channel interleaving. In channel interleaving, each integrated memory controller successively provides a 64-byte cache line of data from the first DIMM on its channel. After the last memory controller - HP ProLiant SL165s | Memory technology evolution: an overview of system memory t - Page 11
Advanced memory technologies Despite the performance improvement in the overall system due to use of SDRAM, the growing performance gap between the memory and processor must be filled by more advanced memory technologies. These technologies, which are described on the following pages, boost the - HP ProLiant SL165s | Memory technology evolution: an overview of system memory t - Page 12
Double transition clocking Standard DRAM transfers one data bit to the bus on the rising edge of the bus clock signal, while DDR-1 uses both the rising and falling edges of the clock to trigger the data transfer to the bus (Figure 10). This technique, known as double transition clocking, delivers - HP ProLiant SL165s | Memory technology evolution: an overview of system memory t - Page 13
184 pins instead of the 168 pins used by standard SDRAM DIMMs. DDR-1 is versatile enough to be used in desktop PCs or servers. To vary the cost of DDR-1 DIMMs for these different markets, memory manufacturers provide unbuffered and registered versions. Unbuffered DDR-1 DIMMs place the load of all - HP ProLiant SL165s | Memory technology evolution: an overview of system memory t - Page 14
. • Fly-by topology (for the commands, addresses, control signals, and clocks) improves signal integrity by reducing the number of stubs and their length. This feature requires the controller to support "write leveling" on DDR-3 DIMMs. • 1.5-V signaling (compared to 1.8 V for DDR-2) for lower power - HP ProLiant SL165s | Memory technology evolution: an overview of system memory t - Page 15
that negatively affects signal integrity. In addition, each supported as the bus speed increases. For example, Figure 14 shows the number of loads supported the number of supported loads drops from not a viable option due to increased cost and board complexity. System designers had two - HP ProLiant SL165s | Memory technology evolution: an overview of system memory t - Page 16
Consequently, JEDEC developed the Fully-Buffered DIMM (FB-DIMM) specification, a serial interface that eliminates the parallel stub-bus topology and allows higher memory bandwidth while maintaining or increasing memory capacity. FB-DIMM architecture The FB-DIMM architecture has serial links between - HP ProLiant SL165s | Memory technology evolution: an overview of system memory t - Page 17
get hotter. Therefore, a heat spreader is required to help draw heat away from the FB-DIMM so it can be cooled more efficiently by the server's internal fans (Figure 16). These concerns are driving the design of AMBs that use 15 to 20 percent less power, even though some manufacturers claim - HP ProLiant SL165s | Memory technology evolution: an overview of system memory t - Page 18
of three key elements: RDRAMs, Rambus application-specific integrated circuits, and an interconnect called the Rambus Channel. the design of the memory controller. Figure 17. Rambus DRAM RDRAM is capable of supporting up to 32 RDRAM devices on one memory channel while maintaining a 1.2-GHz data rate - HP ProLiant SL165s | Memory technology evolution: an overview of system memory t - Page 19
up to twice as much as SDRAM. RDRAM technology offers performance advantages and lower pin count than SDRAM and DDR SDRAM. However, SDRAM and DDR SDRAM offer more memory capacity and lower cost than RDRAM. Importance of using HP-certified memory modules in ProLiant servers Customers should use only - HP ProLiant SL165s | Memory technology evolution: an overview of system memory t - Page 20
Memory Protection Fully-Buffered DIMM technology in HP ProLiant servers Web address http://www.jedec.org http://h18004.www1.hp.com/products/servers/technology/whitepapers/advtechnology.html#mem http://h18004.www1.hp.com/products/servers/technology/whitepapers/advtechnology.html#mem Call to
Memory technology evolution: an overview
of system memory technologies
technology brief, 8
th
edition
Abstract
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2
Introduction
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2
Basic DRAM operation
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2
DRAM storage density and power consumption
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4
Memory access time
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4
Chipsets and system bus timing
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4
Memory bus speed
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5
Burst mode access
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5
SDRAM technology
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6
Bank interleaving
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7
Increased bandwidth
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7
Registered SDRAM modules
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7
DIMM Configurations
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8
Single-sided and double-sided DIMMs
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8
Single-rank, dual-rank, and quad-rank DIMMs
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8
Rank interleaving
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9
Memory channel interleaving
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10
Advanced memory technologies
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11
Double Data Rate SDRAM technologies
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11
DDR-1
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11
DDR-2
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13
DDR-3
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14
Module naming convention and peak bandwidth
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14
Fully-Buffered DIMMs
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15
FB-DIMM architecture
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16
Challenges
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17
Rambus DRAM
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18
Importance of using HP-certified memory modules in ProLiant servers
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19
Conclusion
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19
For more information
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20
Call to action
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20