Intel 520J Data Sheet

Intel 520J - Pentium 4 2.80GHz 800MHz 1MB Socket 775 CPU Manual

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  • Intel 520J | Data Sheet - Page 1
    Intel® Pentium® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531 and 520/521∆ Supporting Hyper-Threading Technology1 Datasheet On 90 nm Process in 775-land LGA Package and supporting Intel® Extended Memory 64 TechnologyΦ May 2005 Document Number: 302351-004
  • Intel 520J | Data Sheet - Page 2
    are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. 1Hyper-Threading Technology requires a computer system with an Intel® Pentium® 4 processor supporting Hyper-Threading Technology and an HT Technology
  • Intel 520J | Data Sheet - Page 3
    22 2.8 Test Access Port (TAP) Connection 23 2.9 FSB Frequency Select Signals (BSEL[2:0 23 2.10 Absolute Maximum and Minimum Ratings 24 2.11 Processor DC Specifications 24 2.12 VCC Overshoot Specification 33 2.12.1 Die Voltage Validation 33 2.13 GTL+ FSB Specifications...34 3 Package Mechanical
  • Intel 520J | Data Sheet - Page 4
    or HALT Snoop State, Grant Snoop State 88 7 Boxed Processor Specifications ...89 7.1 Mechanical Specifications 90 7.1.1 Boxed Processor Cooling Solution Dimensions 90 7.1.2 Boxed Processor Fan Heatsink Weight 91 7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly 91
  • Intel 520J | Data Sheet - Page 5
    Assembly Sketch 35 3-2 Processor Package Drawing 1 36 3-3 Processor Package Drawing 2 37 3-4 Processor Package Drawing 3 38 3-5 Processor Top-Side Marking Example 40 3-6 Processor Top-Side Marking Example for Processors Supporting Intel® EM64T 41 3-7 Processor Land Coordinates (Top View
  • Intel 520J | Data Sheet - Page 6
    18 2-3 FSB Signal Groups...21 2-4 Signal Characteristics ...22 2-5 Signal Reference Voltages ...22 2-6 BSEL[2:0] Frequency Table for BCLK[1:0 23 2-7 Processor DC Absolute Maximum Ratings 24 2-8 Voltage and Current Specifications 25 2-9 VCC Static and Transient Tolerance for 775_VR_CONFIG_04A
  • Intel 520J | Data Sheet - Page 7
    -004 Description • Initial release • Added specifications for processor number 550 with PRB = 0 • Added support for Execute Disable Bit capability • Added Icc Enhanced Auto Halt specifications • Added support for Thermal Monitor 2 • Added specifications for processor number 570 with PRB = 1 • Added
  • Intel 520J | Data Sheet - Page 8
    Contents 8 Datasheet
  • Intel 520J | Data Sheet - Page 9
    2.80 GHz • Supports Hyper-Threading Technology1 (HT Technology) for all frequencies with 800 MHz front side bus (FSB) • Intel® Pentium® 4 processors 571, 561, 551, 541, 531, and 521 support Intel® Extended Memory 64 Technology (EM64T)Φ • Supports Execute Disable Bit capability • Binary compatible
  • Intel 520J | Data Sheet - Page 10
    Contents 10 Datasheet
  • Intel 520J | Data Sheet - Page 11
    . Refer to Section 6.1, for Hyper-Threading Technology configuration details. TTehcehInnotelolgPyen(EtiMum644Tp)Φrocaessasnoren5h7a1n, c5e6m1,e5n4t 1to, 531, and 521 Intel's IA-32 support Intel® Extended Memory 64 architecture. This enhancement enables the processor to execute operating systems
  • Intel 520J | Data Sheet - Page 12
    Introduction 1.1 1.1.1 The Pentium 4 processor on 90 nm process in the LGA775-land package will also include the Execute Disable Bit capability previously available in Intel® Itanium® processors. This feature combined with a support operating system allows memory to be marked as executable or
  • Intel 520J | Data Sheet - Page 13
    /302352.htm Intel® Pentium® 4 Processor on 90 nm Process in the 775-Land Package Thermal Design Guidelines http://developer.intel.com/ design/Pentium4/guides/ 302553.htm Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket Intel® Architecture Software Developer's Manual IA-32
  • Intel 520J | Data Sheet - Page 14
    Introduction 14 Datasheet
  • Intel 520J | Data Sheet - Page 15
    Pentium 4 processor processor remains within the specifications listed in Table 2-8. Failure to do so can result in timing violations or reduced lifetime of the component. For further information and design guidelines, refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775
  • Intel 520J | Data Sheet - Page 16
    Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket. 2.3.2 FSB GTL+ Decoupling The Pentium 4 processor in the 775-land package integrates signal on the Pentium 4 processor in the 775-land package clocking, refer to the CK410/CK410M Clock Synthesizer/Driver Specification.
  • Intel 520J | Data Sheet - Page 17
    2.4 Electrical Specifications Voltage Identification The VID specification for the Pentium 4 processor in the 775-land package is supported by the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage to be
  • Intel 520J | Data Sheet - Page 18
    Electrical Specifications Table 2-2. Voltage Identification Definition VID5 VID4 VID3 VID2 VID1 VID0 VID 0 0 1 0 1 0 0.8375 1 0 1 0 0 1 0.8500 0 0 1 0 0 1 0.8625 1 0 1 0 0 0 0.8750 0 0 1 0 0 0 0.8875 1 0 0 1 1 1 0.9000 0 0 0 1 1 1 0.9125 1 0 0
  • Intel 520J | Data Sheet - Page 19
    Specifications 2.4.1 Phase Lock Loop (PLL) Power and Filter VCCA and VCCIOPLL are power sources required by the PLL clock generators for the Pentium 4 processor in the 775-land package. Since these PLLs are analog, they require low noise power supplies for minimum jitter. Jitter is detrimental to
  • Intel 520J | Data Sheet - Page 20
    to an appropriate signal level. In a system level design, on-die termination has been included on the Pentium 4 processor in the 775-land package to allow signals to be terminated within the processor silicon. Most unused GTL+ inputs should be left as no connects, as GTL+ termination is provided on
  • Intel 520J | Data Sheet - Page 21
    . One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and
  • Intel 520J | Data Sheet - Page 22
    board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects. 3. The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 6.1 for
  • Intel 520J | Data Sheet - Page 23
    Electrical Specifications 2.8 Test Access Port (TAP) Connection Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the Pentium 4 processor in the 775-land package be first in the TAP chain and followed by any other components within
  • Intel 520J | Data Sheet - Page 24
    . Table 2-8 through Table 2-15 list the DC specifications for the Pentium 4 processor in the 775-land package and are valid only while meeting specifications for each parameter. MSR_PLATFORM_BRV bit 18 is a Platform Requirement Bit (PRB) that indicates that the processor has specific platform
  • Intel 520J | Data Sheet - Page 25
    3.40 GHz (PRB = 0) 3.20 GHz (PRB = 0) 3 GHz (PRB = 0) 2.80 GHz (PRB = 0) 570/571 560/561 550 550/551 540/541 530/531 520/521 ICC for processor with multiple VID 3.80 GHZ (PRB = 1) 3.60 GHz (PRB = 1) 3.40 GHz (PRB = 1) 3.40 GHz (PRB = 0) 3.20 GHz (PRB = 0) 3 GHz (PRB = 0) 2.80 GHz (PRB = 0) ICC
  • Intel 520J | Data Sheet - Page 26
    is maximum total current drawn from VTT plane by only the processor. This specification does not include the current coming from RTT (through the signal line). Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket to determine the total ITT drawn by the system. 26
  • Intel 520J | Data Sheet - Page 27
    and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details. 4. Adherence to this
  • Intel 520J | Data Sheet - Page 28
    and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details. 4. Adherence to this
  • Intel 520J | Data Sheet - Page 29
    and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details. 4. Adherence to this
  • Intel 520J | Data Sheet - Page 30
    and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details. 4. Adherence to this
  • Intel 520J | Data Sheet - Page 31
    experience excursions above VTT. However, input signal drivers must comply with the signal quality spec- ifications. 6. The VTT referred to in these 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the voltage range at a receiving
  • Intel 520J | Data Sheet - Page 32
    Current 8 mA - 200 µA 3 VTOL Voltage Tolerance VTT (max) V - NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. These parameters are not tested and are based on design simulations. 3. Leakage to VSS with land held at 2.5 V. Table
  • Intel 520J | Data Sheet - Page 33
    Electrical Specifications 2.12 VCC Overshoot Specification The Pentium 4 processor in the 775-land package can tolerate short processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope. Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775
  • Intel 520J | Data Sheet - Page 34
    , all specifications in this table apply to all processor frequencies. 2. The tolerances for this specification have Intel representative for further details and documentation. 6. These pull-ups are to VTT. 7. RTT is the on-die termination resistance measured at VTT/2 of the GTL+ output driver
  • Intel 520J | Data Sheet - Page 35
    thermal solutions, such as a heatsink. Figure 3-1 shows a sketch of the processor package components and how they are assembled together. Refer to the LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket. The package components shown in Figure 3-1 include the following
  • Intel 520J | Data Sheet - Page 36
    Package Mechanical Specifications Figure 3-2. Processor Package Drawing 1 36 Datasheet
  • Intel 520J | Data Sheet - Page 37
    Figure 3-3. Processor Package Drawing 2 Package Mechanical Specifications Datasheet 37
  • Intel 520J | Data Sheet - Page 38
    Package Mechanical Specifications Figure 3-4. Processor Package Drawing 3 38 Datasheet
  • Intel 520J | Data Sheet - Page 39
    is the maximum force that can be applied by a heatsink retention clip. The clip must also provide the minimum specified load on the processor package. 3. These specifications are based on limited testing for design characterization. Loading limits are for the package only and does not include the
  • Intel 520J | Data Sheet - Page 40
    land package can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide. 3.6 Processor Mass Specification The typical mass of the Pentium 4 processor in the 775-land package is 21.5 g [0.76 oz
  • Intel 520J | Data Sheet - Page 41
    Package Mechanical Specifications Figure 3-6. Processor Top-Side Marking Example for Processors Supporting Intel® EM64T ProcessorNumber/S-Spec/ CountryofAssy Frequency/L2Cache/Bus/ 775_VR_CONFIG_04x FPO 2-DMatrixMark INTEL m © '04 Pentium ® 4 571 SLxxx [COO] 3.80GHZ/1M/800/04B [FPO] ATPO S/N
  • Intel 520J | Data Sheet - Page 42
    Package Mechanical Specifications . Figure 3-7. Processor Land Coordinates (Top View) V /V CC SS 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
  • Intel 520J | Data Sheet - Page 43
    and Signal Descriptions 4 Land Listing and Signal Descriptions 4.1 This chapter provides the processor land assignment and signal descriptions. Processor Land Assignments This section contains the land listings for the Pentium 4 processor in the 775-land package. The landout footprint is shown in
  • Intel 520J | Data Sheet - Page 44
    Land Listing and Signal Descriptions Figure 4-1. Landout Diagram (Top View - Left Side) 30 29 28 AN VCC VCC VSS 27 VSS 26 25 24 23 22 21 20 VCC VCC VSS VSS VCC VCC VSS AM VCC VCC VSS AL VCC VCC VSS AK VSS VSS VSS AJ VSS VSS VSS AH VCC VCC VCC AG VCC VCC VCC AF VSS VSS VSS AE VSS
  • Intel 520J | Data Sheet - Page 45
    Land Listing and Signal Descriptions Figure 4-2. Landout Diagram (Top View - Right Side) 14 13 VCC VSS VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VSS 12 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS 11 10 VCC VSS VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS
  • Intel 520J | Data Sheet - Page 46
    Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A20M# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADS# ADSTB0# ADSTB1# AP0# AP1# BCLK0 Land
  • Intel 520J | Data Sheet - Page 47
    Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# Land
  • Intel 520J | Data Sheet - Page 48
    Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name ITP_CLK1 LINT0 LINT1 LL_ID0 LL_ID1 LOCK# MCERR# MSID0 MSID1 PROCHOT# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
  • Intel 520J | Data Sheet - Page 49
    Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Land Signal Buffer # Type Direction AC26
  • Intel 520J | Data Sheet - Page 50
    Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Land Signal Buffer # Type Direction AK12
  • Intel 520J | Data Sheet - Page 51
    Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Land Signal Buffer # Type Direction K29 Power
  • Intel 520J | Data Sheet - Page 52
    Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land Signal Buffer # Type Direction AA24
  • Intel 520J | Data Sheet - Page 53
    Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land Signal Buffer # Type Direction AJ23
  • Intel 520J | Data Sheet - Page 54
    /Other P23 Power/Other P24 Power/Other P25 Power/Other P26 Power/Other P27 Power/Other P28 Power/Other P29 Power/Other P30 Power/Other P4 Power/Other P7 Power/Other R2 Power/Other R23 Power/Other R24 Power/Other R25 Power/Other R26 Power/Other R27 Power/Other R28 Power
  • Intel 520J | Data Sheet - Page 55
    Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_MB_ REGULATION VSS_SENSE VSSA VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT Land Signal Buffer # Type
  • Intel 520J | Data Sheet - Page 56
    Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 Land Name VSS RS2# D2# D4# VSS D7# DBI0# VSS D8# D9# VSS COMP0 D50#
  • Intel 520J | Data Sheet - Page 57
    Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # C24 C25 C26 C27 C28 C29 C30 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 E2 E3 E4 E5 Land Name VSS VTT VTT VTT VTT VTT VTT RESERVED ADS# VSS HIT# VSS
  • Intel 520J | Data Sheet - Page 58
    Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # F19 F20 F21 F22 F23 F24 F25 F26 F28 F29 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 H1 Land Name VSS D41# D43# VSS RESERVED TESTHI7 TESTHI2 TESTHI0
  • Intel 520J | Data Sheet - Page 59
    Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 K1 K2 K3 K4 K5 K6 K7 K8 K23 K24 K25 K26 K27 K28 K29 K30 L1 L2 L3 L4 L5 L6 L7 Land Name VCC VCC VCC DP0# DP3# VCC VCC VCC VCC VCC VCC VCC VCC VCC
  • Intel 520J | Data Sheet - Page 60
    Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # P1 P2 P3 P4 P5 P6 P7 P8 P23 P24 P25 P26 P27 P28 P29 P30 R1 R2 R3 R4 R5 R6 R7 R8 R23 R24 R25 R26 R27
  • Intel 520J | Data Sheet - Page 61
    Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # W3 W4 W5 W6 W7 W8 W23 W24 W25 W26 W27 W28 W29 W30 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA23 AA24 AA25 AA26 Land Name TESTHI1 VSS A16# A18# VSS VCC VCC VCC VCC VCC VCC
  • Intel 520J | Data Sheet - Page 62
    Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # AD6 AD7 AD8 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30 Land Name A22# VSS VCC
  • Intel 520J | Data Sheet - Page 63
    Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 Land Name VCC VSS
  • Intel 520J | Data Sheet - Page 64
    Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Output Output Output Output 64 Datasheet
  • Intel 520J | Data Sheet - Page 65
    Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # AM27 AM28 AM29 AM30 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 Land Name VSS VSS VCC VCC VSS VSS VCC_SENSE VSS_SENSE VCC_MB_ REGULATION VSS_MB_ REGULATION FC16 VCC VCC VSS VCC VCC VSS VCC VCC
  • Intel 520J | Data Sheet - Page 66
    , the processor masks physical address bit 20 ( processor's address wrap-around at the 1-MB boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction falling edges. Strobes
  • Intel 520J | Data Sheet - Page 67
    by all processor FSB agents and if used, must connect the appropriate pins/lands of all such agents. If the BINIT# driver is enabled during to determine whether the processor is installed in a platform that supports the Pentium 4 processor in the 775-land package. The processor will not operate if
  • Intel 520J | Data Sheet - Page 68
    Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins/ lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals
  • Intel 520J | Data Sheet - Page 69
    DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the support of the feature and enable/disable information, refer to volume 3 of the Intel Architecture Software Developer's Manual and the Intel Processor Identification and the CPUID Instruction
  • Intel 520J | Data Sheet - Page 70
    and continue to execute noncontrol floating-point instructions. If IGNNE# is de-asserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set
  • Intel 520J | Data Sheet - Page 71
    can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary
  • Intel 520J | Data Sheet - Page 72
    the assertion of PWRGOOD. Input TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. Input TRDY# (Target Ready) is asserted by the the processor package to the sense point land U27 as described in the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop Socket
  • Intel 520J | Data Sheet - Page 73
    ID) signals are used to support automatic selection of power supply voltages (VCC). These are open drain signals that are driven by the processor and must be pulled up on the motherboard. Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop Socket 775 for more information. The
  • Intel 520J | Data Sheet - Page 74
    Land Listing and Signal Descriptions 74 Datasheet
  • Intel 520J | Data Sheet - Page 75
    Intel® Pentium® 4 Processor on 90 nm Process in the 775-Land Package Thermal Design Guidelines. Note: The boxed processor processor thermal design guidelines. The Pentium 4 processor in the 775-land package introduces a new methodology for managing processor temperatures which is intended to support
  • Intel 520J | Data Sheet - Page 76
    temperature is defined at the geometric top center of the processor IHS. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained periods of time. Intel recommends that complete thermal solution designs target the Thermal Design
  • Intel 520J | Data Sheet - Page 77
    Thermal Specifications and Design Considerations Table 5-2. Thermal Profile for Processors with PRB = 1 Power (W) 0 2 4 6 8 10 12 .0 59.5 60.0 60.5 61.0 61.5 62.0 62.5 63.0 63.5 64.0 64.5 65.0 65.5 66.0 Figure 5-1. Thermal Profile for Processors with PRB = 1 75.0 Power (W) 90 92 94 96 98 100 102
  • Intel 520J | Data Sheet - Page 78
    Thermal Specifications and Design Considerations Table 5-3. Thermal Profile for Processors with PRB = 0 Power Maximum Tc (W) (°C) Power (W) .3 56 59.9 58 60.4 Figure 5-2. Thermal Profile for Processors with PRB = 0 70.0 Power (W) 60 62 64 66 68 70 72 74 76 78 80 82 84 Maximum Tc
  • Intel 520J | Data Sheet - Page 79
    are meant to help ensure proper operation of the processor. Figure 5-3 illustrates where Intel recommends TC thermal measurements temperature measurement methodology, refer to the should Intel® be made. For detailed guidelines Pentium® 4 Processor on 90 nm on Process in the 775-Land
  • Intel 520J | Data Sheet - Page 80
    drivers, or interrupt handling routines. Thermal Monitor 2 The Pentium 4 processor in the 775-land package also supports processor is unable to service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and kept pending until the processor
  • Intel 520J | Data Sheet - Page 81
    -Demand Mode The Pentium 4 processor in the 775-land package provides an auxiliary mechanism that allows system software to force the processor to reduce its independent of the processor temperature. When using On-Demand mode, the duty cycle of the clock modulation is programmable via bits 3:1 of
  • Intel 520J | Data Sheet - Page 82
    #. Refer to the Intel Architecture Software Developer's Manuals for specific register and programming details. The Pentium 4 processor in the 775-land . Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop Socket 775 for details on implementing the bi-directional PROCHOT# feature
  • Intel 520J | Data Sheet - Page 83
    242 3.33 3.594 Ω 2, 3, 6 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. , as defined, includes the pins of the processor but does not include any socket resistance or a temperature offset can be manually calculated and programmed into an offset
  • Intel 520J | Data Sheet - Page 84
    Thermal Specifications and Design Considerations 84 Datasheet
  • Intel 520J | Data Sheet - Page 85
    hardware. The Pentium 4 processor in the 11]# Disable bus parking A15# Disable Hyper-Threading Technology A31# Symmetric agent arbitration ID processor, depending on each particular state. See Figure 6-1 for a visual representation of the processor low power states. The processor adds support
  • Intel 520J | Data Sheet - Page 86
    can be to either Normal Mode or the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system deasserts the STPCLK
  • Intel 520J | Data Sheet - Page 87
    Features Figure 6-1. Processor Low Power State Machine Normal State Normal execution HALT or MWAIT Instruction and HALT Bus SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will
  • Intel 520J | Data Sheet - Page 88
    will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB). After the snoop is serviced, the processor will return to the Stop-Grant state or HALT Power Down state, as appropriate. Enhanced HALT Snoop State The Enhanced HALT Snoop
  • Intel 520J | Data Sheet - Page 89
    process in the 775-land package will also be offered as a boxed Intel processor. Boxed Intel processors are intended for system integrators who build systems from baseboards and standard components. The boxed Pentium 4 processor in the 775-land package will be supplied with a cooling solution. This
  • Intel 520J | Data Sheet - Page 90
    will be shipped with an unattached fan heatsink. Figure 7-1 shows a mechanical representation of the boxed Pentium 4 processor in the 775-land package. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The physical space requirements and dimensions
  • Intel 520J | Data Sheet - Page 91
    Processor (Overall View) 7.1.2 7.1.3 7.2 7.2.1 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5 and the Intel® Pentium® 4 Processor a matched power header to support the boxed processor. Table 7-1 contains specifications for
  • Intel 520J | Data Sheet - Page 92
    a PWM signal from the motherboard from the 4th pin of the connector labeled as CONTROL. The boxed processor's fan heatsink requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control. The power header on the baseboard must be positioned to allow
  • Intel 520J | Data Sheet - Page 93
    the cooling requirements of the fan heatsink solution used by the boxed processor. Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire
  • Intel 520J | Data Sheet - Page 94
    Boxed Processor Specifications Figure 7-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top View) Figure 7-8. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side View) 94 Datasheet
  • Intel 520J | Data Sheet - Page 95
    is at its maximum. As fan speed increases, so does fan noise levels. Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains cooler then lower set point. These set points, represented in Figure 7-9 and Table 7-2, can vary by a few degrees from fan
  • Intel 520J | Data Sheet - Page 96
    Processor Fan Heatsink Set Point (ºC) Boxed Processor boxed processor fan heatsink Intel has added an option to the boxed processor processor die temperature through the processor actual processor temperature processor Intel® Pentium® 4 Processor on 90 nm Process in the 775-Land
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Intel
®
Pentium
®
4 Processors
570/571, 560/561, 550/551,
540/541, 530/531 and 520/521
∆
Supporting Hyper-Threading
Technology
1
Datasheet
On 90 nm Process in 775-land LGA Package and
supporting Intel
®
Extended Memory 64 Technology
Φ
May 2005
Document Number: 302351-004