Intel BV80605001914AG Specification Update

Intel BV80605001914AG - Processor - 1 x Xeon X3430 Manual

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  • Intel BV80605001914AG | Specification Update - Page 1
    Intel® Xeon® Processor 3400 Series Specification Update May 2010 Reference Number: 322373-009
  • Intel BV80605001914AG | Specification Update - Page 2
    system delivers Intel Turbo Boost Technology. For more information, see http://www.intel.com/technology/turboboost Intel® Hyper-threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology-enabled chipset, BIOS, and operating system. Performance will
  • Intel BV80605001914AG | Specification Update - Page 3
    Contents Contents Revision History ...5 Preface ...6 Summary Tables of Changes 8 Identification Information 16 Errata ...19 Specification Changes 55 Specification Clarifications 56 Documentation Changes 57 § 3 Specification Update
  • Intel BV80605001914AG | Specification Update - Page 4
    Contents 4 Specification Update
  • Intel BV80605001914AG | Specification Update - Page 5
    -006 -007 -008 -009 Initial Release Added Errata AAO101-AAO109. Updated the Processor Identification Table to include two additional SKUs: • Intel® Xeon® Processor X3430 (S-Spec Number: SLBLJ). • Intel® Xeon® Processor L3426 (S-Spec Number: SLBN3). Added Errata AAO110- AAO113. Updated Errata AAO89
  • Intel BV80605001914AG | Specification Update - Page 6
    1 Intel® Xeon® Processor 3400 Series Datasheet - Volume 2 Document Number 322371-003 322372-001 Related Documents Document Title AP-485, Intel® Processor Identification and the CPUID Instruction Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture Intel® 64
  • Intel BV80605001914AG | Specification Update - Page 7
    Products are differentiated by their unique characteristics,e.g., core speed, L2 cache size, package type, etc. as described in the processor identification information table. Read all notes appropriate product specification or user documentation (datasheets, manuals, etc.). 7 Specification Update
  • Intel BV80605001914AG | Specification Update - Page 8
    Tables of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through
  • Intel BV80605001914AG | Specification Update - Page 9
    Intel® Xeon® processor MP with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Celeron® D processor Mobile Intel® Celeron® processor Intel® Pentium® 4 processor Intel® Xeon® processor MP Intel ® Xeon® processor Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading technology
  • Intel BV80605001914AG | Specification Update - Page 10
    ® Atom™ processor 200 series Intel® Atom™ processor N series Intel® Atom™ processor 300 series Intel® Xeon® processor 7400 series Intel® Core™ i7-900 desktop processor Extreme Edition series and Intel® Core™ i7-900 desktop processor series Intel® Xeon® processor 5500 series Intel® Pentium® dual-core
  • Intel BV80605001914AG | Specification Update - Page 11
    Memory-Ordering Violations Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher Priority Interrupts/Exceptions and May Push the Wrong Address Onto the Stack Performance Monitor SSE Retired Instructions May Return Incorrect Values Premature Execution of a Load Operation Prior to
  • Intel BV80605001914AG | Specification Update - Page 12
    Reset of IA32_APERF/IA32_MPERF Counters on Overflow Does Not Work Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in Stuck Core Operating Ratio PECI Does Not Support PCI Configuration Reads/Writes to Misaligned Addresses OVER Bit for IA32_MCi_STATUS Register May Get
  • Intel BV80605001914AG | Specification Update - Page 13
    Processor Forward Progress Mechanism Interacting With Certain MSR/CSR Writes May Cause Unpredictable System Behavior Performance Monitor Event Offcore_response_0 (B7H) Does Not Count NT Stores to Local DRAM Correctly EFLAGS Discrepancy on Page Faults and on EPT Core by One Instruction Malformed PCIe
  • Intel BV80605001914AG | Specification Update - Page 14
    or Hang a Subsequent Interrupt-Remap-Cache Invalidation Command S1 Entry May Cause Cores to Exit C3 or C6 C-State Multiple Performance Monitor Interrupts are Possible on Overflow of IA32_FIXED_CTR2 LBRs May Not be Initialized During Power-On Reset of the Processor Unexpected Interrupts May Occur on
  • Intel BV80605001914AG | Specification Update - Page 15
    May be Incorrect PMIs During Core C6 Transitions May Cause the System to Hang IA32_MC8_CTL2 MSR is Not Cleared on Processor Warm Reset The TPM's Locality Bit Address Size in 64-bit Mode IOTLB Invalidations Not Completing on Intel ® VT-d Engine for Integrated High Definition Audio IO_SMI Indication in
  • Intel BV80605001914AG | Specification Update - Page 16
    reset is equivalent to the processor signature output value in the EAX register. Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register. The Intel Xeon processor 3400 series can be identified
  • Intel BV80605001914AG | Specification Update - Page 17
    Number Stepping Processor Signature SLBPT X3480 B-1 106E5h SLBJH X3470 B-1 106E5h SLBJK X3460 B-1 106E5h SLBLD X3450 B-1 106E5h SLBLF X3440 B-1 106E5h Core Frequency (GHz) / DDR3 (MHz) 3.06 / 1333 2.93 / 1333 2.80 / 1333 2.66 / 1333 2.53 / 1333 Max Intel® Turbo Boost Technology
  • Intel BV80605001914AG | Specification Update - Page 18
    Cache Size (MB) 8 8 Notes 8 1, 4, 5, 6 3, 4, 5, 6, 7 Notes: 1. This processor has TDP of 95W and meets the 1156_VR_CONF_09B VR Configuration. 2. This column indicates maximum Intel® Turbo Boost Technology frequency (GHz) for 4, 3, 2, or 1 cores active respectively. 3. Intel® Hyper-Threading
  • Intel BV80605001914AG | Specification Update - Page 19
    described in the Software Developers Manual section "Out- of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors" the processor performs REP MOVS or REP STOS as fast strings. Due to this erratum fast string REP MOVS/REP STOS instructions that cross page boundaries
  • Intel BV80605001914AG | Specification Update - Page 20
    , see the Summary Tables of Changes. AAO4. Performance Monitor SSE Retired Instructions May Return Incorrect Values Problem: Performance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is used to track retired SSE instructions. Due to this erratum, the processor may also count other types of
  • Intel BV80605001914AG | Specification Update - Page 21
    a Load Operation Prior to Exception Handler Invocation Problem: If any of the below circumstances occur, it is possible that the load portion of the instruction will have executed before the exception handler is entered. • If an instruction that performs a memory load causes a code segment limit
  • Intel BV80605001914AG | Specification Update - Page 22
    Problem: A partial memory state save of the 512-byte FXSAVE image or a partial memory state restore of the FXRSTOR image may occur if a memory address exceeds the 64KB limit while the processor 3 above mentioned debug support facilities are used. Implication: the same instruction Workaround: None
  • Intel BV80605001914AG | Specification Update - Page 23
    IA-32 Intel® Architecture Software Developer's Manual, Vol. 1, Basic Architecture, for information on the usage of the ENTER instructions. This Fault (#GP) for Instructions Greater than 15 Bytes May be Preempted Problem: When the processor encounters an instruction that is greater than 15
  • Intel BV80605001914AG | Specification Update - Page 24
    Occurs in 64-bit Mode Problem: An exception/interrupt event should processor will hang. The local xAPIC's address space must be uncached. The MONITOR instruction only functions correctly if the specified linear address range is of the type write-back. CLFLUSH flushes data from the cache. Intel
  • Intel BV80605001914AG | Specification Update - Page 25
    the first FAR JMP. Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide, Part 1, in the Report the Monitoring Hardware as Armed Problem: A processor write to the address range armed by the MONITOR instruction may not immediately trigger the monitoring
  • Intel BV80605001914AG | Specification Update - Page 26
    . Improper Parity Error Signaled in the IQ Following Reset When a Code Breakpoint is Set on a #GP Instruction Problem: While coming out of cold reset or exiting from C6, if the processor encounters an instruction longer than 15 bytes (which causes a #GP) and a code breakpoint is enabled on that
  • Intel BV80605001914AG | Specification Update - Page 27
    Changes. AAO24. Problem: IA32_MPERF Counter Stops Counting During On-Demand TM1 According to the Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide, the ratio of IA32_MPERF (MSR E7H) to IA32_APERF (MSR E8H) should reflect actual performance while TM1
  • Intel BV80605001914AG | Specification Update - Page 28
    , see the Summary Tables of Changes. AAO28. Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in Stuck Core Operating Ratio Problem: If a processor is at its TCC (Thermal Control Circuit) activation temperature and then Thermal Monitor is disabled by a write to
  • Intel BV80605001914AG | Specification Update - Page 29
    EOI) the bit for the vector will be left set in the in-service register and mask all interrupts at the same or lower priority. Workaround: steppings affected, see the Summary Tables of Changes. AAO32. Problem: Faulting MMX Instruction May Incorrectly Update x87 FPU Tag Word Under a specific set
  • Intel BV80605001914AG | Specification Update - Page 30
    VMCS and Referenced Data Structures Problem: Bits 53:50 of the IA32_VMX_BASIC MSR report the memory type that the processor uses to access the VMCS and Software should not execute a floating point instruction directly after a MOV SS or POP SS instruction. Status: For the steppings affected, see
  • Intel BV80605001914AG | Specification Update - Page 31
    Monitor Event MISALIGN_MEM_REF May Over Count Problem: The MISALIGN_MEM_REF Performance Monitoring (Event 05H) may over count memory misalignment events, possibly by orders of magnitude. Implication: Software relying on MISALIGN_MEM_REF to count cache line splits for optimization purposes may
  • Intel BV80605001914AG | Specification Update - Page 32
    Received while All Cores in C6 Problem: If all logical processors in a core are in C6, on the core servicing the external interrupt. Intel has not processor thread begins a transition to a low power Cstate, the xAPIC may generate two interrupts instead of the expected one when the processor
  • Intel BV80605001914AG | Specification Update - Page 33
    A PEBS record may be saved after an RSM instruction due to the associated performance counter detecting the monitored event during SMM; even when Incorrect Information When the First Instruction After a MOV SS,r/m or POP SS is a Store Problem: Normally, each instruction clears the changes in DR6
  • Intel BV80605001914AG | Specification Update - Page 34
    AAO49. Performance Monitor Interrupts Generated From Uncore Fixed Counters (394H) May be Ignored Problem: Performance monitor performance monitor counters 3B0H-3BFH are not programmed. Implication: This erratum blocks a usage model in which each of the cores can sample its own performance
  • Intel BV80605001914AG | Specification Update - Page 35
    May Count Higher than Expected Problem: Performance Monitoring counter INST_RETIRED.STORES (Event: C0H) is used to track retired instructions which contain a store operation. Due to this erratum, the processor may also count other types of instructions including WRMSR and MFENCE. Implication
  • Intel BV80605001914AG | Specification Update - Page 36
    Intel 64 and IA-32 Intel® Architecture Software Developer's Manual, Volume 3A, in the section titled Programming the PAT. Intel Performance Monitor Counters May Count Incorrectly Problem: Under certain circumstances, a general purpose performance counter, IA32_PMC0-4 (C1H - C4H), may count at core
  • Intel BV80605001914AG | Specification Update - Page 37
    a Translation Change Problem: This erratum is regarding the case where paging structures are modified to change a linear address from writable to non-writable without software performing an appropriate TLB invalidation. When a subsequent access to that address by a specific instruction (ADD, AND
  • Intel BV80605001914AG | Specification Update - Page 38
    2x Refresh is Enabled May Result in a System Hang Problem: If ASR_PRESENT (MC_CHANNEL_{0,1}_REFRESH_THROTTLE_SUPPORT CSR function 0, offset 68H, bit [0], Auto Self Refresh Present) is clear which indicates that high temperature operation is not supported on the DRAM, the memory controller will not
  • Intel BV80605001914AG | Specification Update - Page 39
    Yellow Error Indication May be Overwritten by Other Corrected Errors Problem: A corrected cache hierarchy data or tag error that is reported with . AAO64. PSI# Signal May Incorrectly be Left Asserted Problem: When some of the cores in the processor are in C3/C6 state, the PSI# (Power Status
  • Intel BV80605001914AG | Specification Update - Page 40
    the Summary Tables of Changes. AAO67. Rapid Core C3/C6 Transitions May Cause Unpredictable System Behavior Problem: Under a complex set of internal conditions, cores rapidly performing C3/C6 transitions in a system with Intel® Hyper-Threading Technology enabled may cause a machine check error
  • Intel BV80605001914AG | Specification Update - Page 41
    (bits[1:0] of PMCSR) when these states are not supported. Implication: Given that the device does not support the D1 and D2 states, attempts to write those states to Registers May Fail When Processor is Transitioning to/from Package C6 Power State Problem: A PECI (Platform Environment Control
  • Intel BV80605001914AG | Specification Update - Page 42
    , see the Summary Tables of Changes. AAO75. PMIs May be Lost During Core C6 Transitions Problem: If a performance monitoring counter overflows and causes a PMI (Performance Monitoring Interrupt) at the same time that the core is entering C6, then the PMI may be lost. Implication: PMIs may
  • Intel BV80605001914AG | Specification Update - Page 43
    Signaled Earlier Than Expected Problem: x87 instructions that trigger #MF normally service interrupts before the #MF. Due to this erratum, if an instruction that triggers #MF is executed while Enhanced Intel SpeedStep® Technology transitions, Intel® Turbo Boost Technology transitions, or Thermal
  • Intel BV80605001914AG | Specification Update - Page 44
    Problem: Locked instructions whose memory reference is split across cache line boundaries and are aborted on PCI behind Intel® 5 Series Chipset and Intel During Package C6 Problem: PECI (Platform Environment Control Interface) MbxSend() requests may become blocked when the processor is in package
  • Intel BV80605001914AG | Specification Update - Page 45
    AAO86. S1 Entry May Cause Cores to Exit C3 or C6 C-State Problem: Under specific circumstances, S1 entry may cause a logical processor to spuriously wake up from . Multiple Performance Monitor Interrupts are Possible on Overflow of IA32_FIXED_CTR2 Problem: When multiple performance counters are
  • Intel BV80605001914AG | Specification Update - Page 46
    of the SSTE32882 Registering Clock Driver with Parity and Quad Chip T-states, C1E, or Adaptive Thermal Throttling Problem: The "From" address associated with the LBR Intel recommends discarding processor temperature values less than -100 or greater than 0, and the use of appropriate temperature
  • Intel BV80605001914AG | Specification Update - Page 47
    : For the steppings affected, see the Summary Tables of Changes. AAO94. PECI Mailbox Commands During Package C6 Idle State Transitions May Result in Unpredictable Processor Behavior Problem: If a PECI (Platform Environment Control Interface) mailbox command is executed at the same time that the
  • Intel BV80605001914AG | Specification Update - Page 48
    and the processor and counter are configured as follows: • Intel® Hyper-Threading Technology is enabled Problem: When the No_Soft_Reset bit in the Power Management Control and Status Register (PMCSR; Bus 0; Devices 0, 3, 4, 5; Function 0; Offset 0xE4; Bit 3) is cleared the device should perform
  • Intel BV80605001914AG | Specification Update - Page 49
    , whether it is blocked or can forward. In addition this event does not count for specific threads correctly. Implication: If Intel® Hyper-Threading Technology is disabled, the Performance Monitor events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA may indicate a higher occurrence of loads blocked by
  • Intel BV80605001914AG | Specification Update - Page 50
    Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions Problem: Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H) counts transitions from x87 Floating Point (FP) to MMX™ instructions System Reset Problem: During power-up, the processor may improperly
  • Intel BV80605001914AG | Specification Update - Page 51
    Problem: When a debug exception is signaled on a load that crosses cache lines Problem: In a complex set of internal conditions when the processor exits from Core C6 state, it is possible that an interrupt may be dropped. Implication: Due to this erratum, an interrupt may be dropped. Intel
  • Intel BV80605001914AG | Specification Update - Page 52
    May Cause the System to Hang Problem: If a performance monitoring counter overflows and causes a PMI (Performance Monitoring Interrupt) at the same time that the core enters C6, then this may cause the system to hang. Implication: Due to this erratum, the processor may hang when a PMI coincides
  • Intel BV80605001914AG | Specification Update - Page 53
    Problem: The FP (Floating Point) Data Operand Pointer is the effective address of the operand associated with the last non-control FP instruction executed by the processor in this way is not a normal programming practice. Intel has not observed this erratum with any commercially available software
  • Intel BV80605001914AG | Specification Update - Page 54
    Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 54 Specification Update
  • Intel BV80605001914AG | Specification Update - Page 55
    documents: • Intel® Xeon® Processor 3400 Series Datasheet - Volumes 1 and 2 • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A: Instruction Set Reference Manual A-M • Intel® 64 and
  • Intel BV80605001914AG | Specification Update - Page 56
    documents: • Intel® Xeon® Processor 3400 Series Datasheet - Volumes 1 and 2 • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A: Instruction Set Reference Manual A-M • Intel® 64 and
  • Intel BV80605001914AG | Specification Update - Page 57
    documents: • Intel® Xeon® Processor 3400 Series Datasheet - Volumes 1 and 2 • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A: Instruction Set Reference Manual A-M • Intel® 64 and
  • Intel BV80605001914AG | Specification Update - Page 58
    Intel® Xeon® Processor 3400 Series (Lynnfield) DateNDA September 2009 RevisionNumberNDA 001 Ref_Num_NDA_LFD CDI / IBL #: 422224 Ref_Num_NDA_LFD_SVR CDI / IBL #: 422225 DatePUB October 2009 RevisionNumberPUB 001 ReferenceNumberPUB TBD Other Variables: Title Intel® Core™ i7 Processor
  • Intel BV80605001914AG | Specification Update - Page 59
    59 Specification Update, October 2009
  • Intel BV80605001914AG | Specification Update - Page 60
    60 Specification Update, March 2008
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    61 Specification Update, October 2009
  • Intel BV80605001914AG | Specification Update - Page 62
    62 Specification Update, March 2008
  • Intel BV80605001914AG | Specification Update - Page 63
    Revision History ...5 Preface ...6 Summary Tables of Changes 8 Identification Information 16 Errata ...19 Specification Changes 55 Specification Clarifications 56 Documentation Changes 57 63 Specification Update,
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Reference Number:
322373-009
Intel
®
Xeon
®
Processor 3400
Series
Specification Update
May 2010