Intel BV80605001914AG Data Sheet

Intel BV80605001914AG - Processor - 1 x Xeon X3430 Manual

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  • Intel BV80605001914AG | Data Sheet - Page 1
    Intel® Xeon® Processor 3400 Series Datasheet - Volume 1 June 2010 Document Number: 322371-003
  • Intel BV80605001914AG | Data Sheet - Page 2
    specific hardware and software you use. For more information including details on which processors support HT Technology, see http://www.intel.com/info/hyperthreading. 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers
  • Intel BV80605001914AG | Data Sheet - Page 3
    (DMI 13 1.2.4 Platform Environment Control Interface (PECI 14 1.3 Power Management Support 14 1.3.1 Processor Core 14 1.3.2 System 14 1.3.3 Memory Controller 14 1.3.4 PCI Express 14 1.4 Thermal Management Support 15 1.5 Package ...15 1.6 Terminology ...15 1.7 Related Documents 17
  • Intel BV80605001914AG | Data Sheet - Page 4
    32 3.1.5 Intel® VT-d Features Not Supported 33 3.2 Intel® Trusted Execution Technology (Intel® TXT 33 3.3 Intel® Hyper-Threading Technology 34 3.4 Intel® Turbo Boost Technology 34 4 Power Management 35 4.1 ACPI States Supported 35 4.1.1 System States 35 4.1.2 Processor Core/Package Idle
  • Intel BV80605001914AG | Data Sheet - Page 5
    1-1 Intel® Xeon® Processor 3400 Series Supported Memory Summary 11 1-2 Related Documents 17 2-1 Supported DIMM Module Configurations 20 2-2 DDR3 System Memory Timing Support 21 2-3 System Memory Pre-Charge Power Down Support 24 2-4 Processor Reference Clock Requirements 29 4-1 Processor Core
  • Intel BV80605001914AG | Data Sheet - Page 6
    72 7-8 DDR3 Signal Group DC Specifications 74 7-9 Control Sideband and TAP Signal Group DC Specifications 75 7-10 PCI Express* DC Specifications 76 7-11 PECI DC Electrical Limits 77 8-1 Signals Not Used by the Intel® Xeon® Processor 3400 Series 79 8-2 Processor Pin List by Pin Name 84
  • Intel BV80605001914AG | Data Sheet - Page 7
    Revision History Revision Number 001 002 003 Description • Initial release • Added workstation information • Added Intel Xeon X3480 processor § § Date September 2009 January 2010 June 2010 Datasheet, Volume 1 7
  • Intel BV80605001914AG | Data Sheet - Page 8
    8 Datasheet, Volume 1
  • Intel BV80605001914AG | Data Sheet - Page 9
    Introduction Note: Note: Note: Note: The Intel® Xeon® processor 3400 series are the next generation of 64-bit, multi-core processors built on 45-nanometer process technology. Based on the low-power/highperformance Intel microarchitecture, the processor is designed for a two-chip platform, instead
  • Intel BV80605001914AG | Data Sheet - Page 10
    Introduction Figure 1-1. Intel® Xeon® Processor 3400 Series Platform Diagram Discrete Graphics (PEG) PCI Express* 1x16 OR PCI Express* 2 x 8 OR PCI Express* 4x4 Not e: Support ed PCI Express conf igurat ions vary by SKU. Quad Core CPU w it h Int egrat ed Memory Cont roller Processor DMI PECI
  • Intel BV80605001914AG | Data Sheet - Page 11
    Intel® 64 Architecture • Execute Disable Bit • Intel® Turbo Boost Technology Some technologies may not be enabled on all processor SKUs. Refer to the processor specification update for details. Intel® Active Management Technology 6.0 is not supported on the Intel Xeon processor 3400 series for Intel
  • Intel BV80605001914AG | Data Sheet - Page 12
    - Command Overlap - Out-of-Order Scheduling PCI Express* • The processor PCI Express* port(s) are fully-compliant with the PCI Express Base Specification, Revision 2.0. • Intel® Xeon® processor 3400 series with the Intel® 3450 Chipset supports: - One 16-lane PCI Express port intended for graphics
  • Intel BV80605001914AG | Data Sheet - Page 13
    64-bit downstream address format, but the processor never generates an address above 64 GB (Bits 63:36 will always be zeros). • 64-bit upstream address format, but the processor PCI Express Base Specification. • Dynamic to-point DMI interface to PCH is supported. • Raw bit-rate on the data pins of 2.5
  • Intel BV80605001914AG | Data Sheet - Page 14
    and a PECI master, usually the PCH. Power Management Support Processor Core • Full support of ACPI C-states as implemented by the following processor C-states: - C0, C1, C1E, C3, C6 • Enhanced Intel SpeedStep® Technology System • S0, S1, S4, S5 Memory Controller • Conditional self-refresh • Dynamic
  • Intel BV80605001914AG | Data Sheet - Page 15
    use an ICH component. Integrated Memory Controller 64-bit memory extensions to the IA-32 architecture. The processor supports Intel® Hyper-Threading Technology (Intel® HT Technology) that allows an execution core to function as two logical processors. Intel® Turbo Boost Technology is a feature that
  • Intel BV80605001914AG | Data Sheet - Page 16
    using DMA remapping, a key feature of Intel VT-d. Processor virtualization which when used in conjunction with specifications. The 64-bit multi-core component (package) The term "processor core" refers to Si die itself which can contain multiple execution cores. Each execution core has an instruction
  • Intel BV80605001914AG | Data Sheet - Page 17
    , Revision 2.0 DDR3 SDRAM Specification Display Port Specification Intel® 64 and IA-32 Architectures Software Developer's Manuals Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System
  • Intel BV80605001914AG | Data Sheet - Page 18
    Introduction 18 Datasheet, Volume 1
  • Intel BV80605001914AG | Data Sheet - Page 19
    supported by the processor. System Memory Interface System Memory Technology Supported The Integrated Memory Controller (IMC) supports DDR3 protocols with two independent, 64-bit wide channels. Refer to Section 1.2.1 for details on the type of memory supported. • Supported ECC • Intel 3400 and 3420
  • Intel BV80605001914AG | Data Sheet - Page 20
    DRAM Organization # of DRAM Devices # of Physical Device Ranks # of Row/Col Address Bits # of Banks Inside DRAM Intel 3450 Chipset Platforms with Intel Xeon® Processor 3400 Series Skus: Unbuffered/ECC Supported DIMM Module Configurations 1 GB 1 Gb 128 M X 8 8 1 14/10 8 2 GB 1 Gb 128
  • Intel BV80605001914AG | Data Sheet - Page 21
    a new command may be issued every 2 clocks. Command launch mode programming depends on the transfer rate and memory configuration. DDR3 System Memory Timing Support Transfer Rate (MT/s) (ttCCKL ) (ttRCCKD) (ttRCKP) CWL (tCK) Unbuffered DIMM CMD Mode Registered DIMM CMD Mode Notes 1066 1333
  • Intel BV80605001914AG | Data Sheet - Page 22
    Flex Memory Technology Mode The IMC supports Intel Flex Memory Technology mode. This mode combines the advantages on real world applications. Addresses are ping-ponged between the channels after each cache line (64-byte boundary). If there are two requests, and the second request is to an address
  • Intel BV80605001914AG | Data Sheet - Page 23
    , bandwidth is limited to a single channel. This mode is used when Intel Flex Memory Technology is disabled and both Channel A and Channel B DIMM connectors the SPD registers on the memory modules. The system memory controller supports one or two DIMM connectors per channel for unbuffered DIMMs or up
  • Intel BV80605001914AG | Data Sheet - Page 24
    Scheduling, Command Overlap, and Out-of-Order Scheduling Intel FMA technology enhancements. 2.1.5.1 Just-in-Time Command Scheduling after entering pre-charge power down Table 2-3. System Memory Pre-Charge Power Down Support DIMM per Channel Configuration One Two One Two or Three One or Two
  • Intel BV80605001914AG | Data Sheet - Page 25
    Specification for details of PCI Express. The number of PCI Express controllers available is dependent on the platform: • Intel Xeon processor 3400 series with the Intel 3450 Chipset: 1 x16 PCI Express Graphics or 2x8 PCI Express Graphics are supported. • Intel Xeon processor 3400 series with Intel
  • Intel BV80605001914AG | Data Sheet - Page 26
    The Physical Layer includes all circuitry for interface operation, including driver and input buffers, parallel-to-serial and serial-to-parallel conversion Layer exchanges data with the Data Link Layer in an implementation-specific format, and is responsible for converting this to an appropriate
  • Intel BV80605001914AG | Data Sheet - Page 27
    host processor to PCI Express configuration cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is recommended that system software access the enhanced configuration space using 32bit operations (32-bit aligned) only. See the PCI Express Base Specification for details
  • Intel BV80605001914AG | Data Sheet - Page 28
    enumeration, such that configuration of the device is neither possible nor necessary. Direct Media Interface (DMI) DMI connects the processor and the PCH chip-to-chip. The DMI is similar to a four-lane PCI Express supporting up to 1 GB/s of bandwidth in each direction. Only DMI x4 configuration is
  • Intel BV80605001914AG | Data Sheet - Page 29
    other information to the PECI master. • Read averaged Digital Thermal Sensor (DTS) values for fan speed control. Interface Clocking Internal Clocking Requirements Table 2-4. Processor Reference Clock Requirements Reference Input Clocks BCLK[0]/BCLK#[0] PEG_CLK/PEG_CLK# Input Frequency 133 MHz
  • Intel BV80605001914AG | Data Sheet - Page 30
    Interfaces 30 Datasheet, Volume 1
  • Intel BV80605001914AG | Data Sheet - Page 31
    performance and robustness. Intel VT-x specifications and functional descriptions are included in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3B and is available at: http://www.intel.com/products/processor/manuals/index.htm. The Intel VT-d spec and other VT documents
  • Intel BV80605001914AG | Data Sheet - Page 32
    a guest - The feature aids VMM developers in flexibility and Quality of Service (QoS) guarantees • Descriptor-Table Exiting - Descriptor-table exiting allows a . Intel® VT-d Features The processor supports the following Intel VT-d features: • 48-bit maximum guest address width and 36-bit maximum
  • Intel BV80605001914AG | Data Sheet - Page 33
    ® VT-d Features Not Supported The following features are not supported by the processor with Intel VT-d: • No support for PCISIG endpoint caching (ATS) • No support for interrupt remapping • No support for advance fault reporting • No support for super pages • No support for 1 or 2 level page walks
  • Intel BV80605001914AG | Data Sheet - Page 34
    number of active cores. No special hardware support is necessary for Intel Turbo Boost Technology. BIOS and the operating system can enable or disable Intel Turbo Boost Technology. Intel Turbo Boost Technology may not be available on all SKUs. Refer to the processor specification update for details
  • Intel BV80605001914AG | Data Sheet - Page 35
    /Package Idle States Table 4-1. Processor Core/Package State Support State C0 C1 C1E C3 C6 Description Active mode, processor executing code. AutoHALT state. AutoHALT state with lowest frequency and voltage operating point. Execution cores in C3 flush their L1 instruction cache, L1 data cache
  • Intel BV80605001914AG | Data Sheet - Page 36
    Sleep Deep Power Down Suspend to RAM Suspend to Disk Soft Off Hard off 4.2 Processor Core Power Management While executing code, Enhanced Intel SpeedStep Technology optimizes the processor's frequency and core voltage based on workload. Each frequency and voltage operating point is defined by ACPI
  • Intel BV80605001914AG | Data Sheet - Page 37
    the thread, processor core, and processor package level. Thread level C-states are available if Intel Hyper-Threading Technology is enabled. Figure 4-1. Idle Power Management Breakdown of the Processor Cores Thread 0 Thread 1 Thread 0 Thread 1 Core 0 State Core 1 State Processor Package State
  • Intel BV80605001914AG | Data Sheet - Page 38
    C-states, a transition to and from C0 is required before entering any other C-state. Table 4-3. Coordination of Thread Power States at the Core Level Processor Core Thread 1 C-State C0 C1 C3 C6 C0 C0 C0 C0 C0 C1 C0 Thread 0 C3 C0 C11 C11 C11 C3 C11 C3 C6 C0 C11
  • Intel BV80605001914AG | Data Sheet - Page 39
    instruction (for C1 and C1E). However, software may make C-state requests using the legacy method of I/O reads from the ACPI-defined processor clock control registers, referred to as P_LVLx. This method of requesting C-states provides legacy support MWAIT instruction. • For core C1/C1E, and core C3,
  • Intel BV80605001914AG | Data Sheet - Page 40
    instruction. A System Management Interrupt (SMI) handler returns execution to either Normal state or the C1/C1E state. See the Intel® 64 and IA-32 Architecture Software Developer's Manual, Volume 3A/3B: System Programmer's Guide for more information. While a core , the processor supports C-state
  • Intel BV80605001914AG | Data Sheet - Page 41
    requests a higher power C-state, the memory access or snoop request is serviced and the package remains in the higher power C-state. Table 4-5 shows an example package C-state resolution for a dual-core processor. Figure 4-3 summarizes package C-state transitions. Table 4-5. Coordination of
  • Intel BV80605001914AG | Data Sheet - Page 42
    No additional power reduction actions are taken in the package C1 state. However, if the C1E sub-state is enabled, the processor automatically transitions to the lowest supported core clock frequency, followed by a reduction in voltage. The package enters the C1 low power state when: • At least one
  • Intel BV80605001914AG | Data Sheet - Page 43
    C3. In package C3-state, the L3 shared cache is snoopable. Package C6 State A processor enters the package C6 low power state when: • At least one core is in the C6 state. • The other cores are in a C6 state, and the processor has been granted permission by the platform. In package C6 state, all
  • Intel BV80605001914AG | Data Sheet - Page 44
    signals, which the SDRAM controller supports. The processor drives four CKE pins to perform as long as there are no memory requests to service. The target usage is shown in Table 4-6. Table DRAM devices in a power down state. The processor core controller can be configured to put the devices in
  • Intel BV80605001914AG | Data Sheet - Page 45
    DIMM slots. The I/O buffer for an unused signal should be tristated (output driver disabled), the input receiver (differential sense-amp) should be disabled, and any is disabled). PCI Express* Power Management • Active power management support using L0s, and L1 states. • All inputs and outputs disabled
  • Intel BV80605001914AG | Data Sheet - Page 46
    Power Management 46 Datasheet, Volume 1
  • Intel BV80605001914AG | Data Sheet - Page 47
    Thermal Management 5 Thermal Management For thermal specifications and design guidelines, refer to the appropriate Thermal and Mechanical Specifications and Design Guidelines (see Section 1.7). § § Datasheet, Volume 1 47
  • Intel BV80605001914AG | Data Sheet - Page 48
    Thermal Management 48 Datasheet, Volume 1
  • Intel BV80605001914AG | Data Sheet - Page 49
    Signal Description 6 Signal Description This chapter describes the processor signals. They are arranged in functional groups according Environment AC Specifications and are AC Coupled. The buffers are not 3.3 V tolerant. Refer to the PCI Express Specification. Intel Flexible Display Interface
  • Intel BV80605001914AG | Data Sheet - Page 50
    SDRAM rank. These signals are only used for processors and platforms that have Registered DIMM support. These signals are used to select particular for every data byte lane. Note: These signals are not used by the Intel Xeon processor 3400 series. They are connected to VSS on the package. Data Bus:
  • Intel BV80605001914AG | Data Sheet - Page 51
    rank. These signals are only used for processors and platforms that have Registered DIMM support. These signals are used to select particular every data byte lane. Note: These signals are not used by the Intel Xeon processor package. 3400 series. They are connected to VSS on the Data
  • Intel BV80605001914AG | Data Sheet - Page 52
    a default value of 1 if not terminated on the board. • CFG[1:0]: PCI Express Bifurcation Intel Xeon® processor 3400 series: 11 = 1 x16 PCI Express 10 = 2 x8 PCI Express 01 = 4 x4 PCI Express (requires Intel 3420 or 3400 Chipset) 00 = Reserved • CFG[2]: Reserved configuration land. A test point may
  • Intel BV80605001914AG | Data Sheet - Page 53
    RSVD_TP SM_DRAMRST# Reset In: When asserted, this signal will asynchronously reset the processor logic. This signal is connected to the I PLTRST# output of the PCH. RESERVED. Must be left unconnected on the board. Intel does not recommend a test point on the board for this land. RESERVED
  • Intel BV80605001914AG | Data Sheet - Page 54
    clock is used to generate the clocks necessary for the support of PCI Express. This also is the reference clock for Intel® Flexible Display Interface. Direction I I O I Type will be used by future processors that are compatible with LGA 1156 platforms. Intel® Flexible Display Interface Signal
  • Intel BV80605001914AG | Data Sheet - Page 55
    . TDO_M (Test Data Out) transfers serial test data out of the processor. TDO_M provides the serial output needed for JTAG specification support. TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must
  • Intel BV80605001914AG | Data Sheet - Page 56
    Circuit. This signal does not have on-die termination and must be terminated on the system board. Processor Power Status Indicator: This signal is asserted when maximum possible processor core current consumption is less than 15 A. Assertion of this signal is an indication that the VR controller
  • Intel BV80605001914AG | Data Sheet - Page 57
    turned on until they come within specification. The signal must then transition monotonically to a high state. Note that it is not valid for VTTPWRGOOD to be de-asserted while VCCPWRGOOD_0 and VCCPWRGOOD_1 are asserted. Direction O I O I I 6.11 Processor Core Power Signals Type Asynch CMOS Asynch
  • Intel BV80605001914AG | Data Sheet - Page 58
    Processor Core Power Signals (Sheet 2 of 2) Signal Name VID[7:6] VID[5:3]/CSC[2:0] VID[2:0]/MSID[2:0] VSS_SENSE VSS_SENSE_VTT VTT VTT_SELECT VTT_SENSE Description VID[7:0] (Voltage ID) are used to support of VTTPWRGOOD). CSC[2:0]-Current Sense Configuration bits, for ISENSE gain setting. See
  • Intel BV80605001914AG | Data Sheet - Page 59
    not used by the processor. It is connected to VSS on the package. GFX_VID[6:0] (Voltage ID) pins are used to support automatic selection of not used by the processor. It is connected to VSS on the package. Graphics core power supply. Note: These signals are not used by the processor. They are no
  • Intel BV80605001914AG | Data Sheet - Page 60
    Signal Description 6.13 Ground and NCTF Table 6-15. Ground and NCTF Signal Name VSS CGC_TP_NCTF Description VSS are the ground pins for the processor and should be connected to the system ground plane. Corner Ground Connection: This land may be used to test for connection to ground. A test point
  • Intel BV80605001914AG | Data Sheet - Page 61
    entering an idle condition from a running condition. To keep voltages within specification, output decoupling must be properly designed. Design the board to ensure that the voltage provided to the processor remains within the specifications listed in Table 7-5. Failure to do so can result in timing
  • Intel BV80605001914AG | Data Sheet - Page 62
    push/pull drivers. Refer to Table 7-9 for the DC specifications for specifications are set so that one voltage regulator can operate with all supported frequencies. Individual processor processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core
  • Intel BV80605001914AG | Data Sheet - Page 63
    Electrical Specifications Table 7-1. VRD 11.1/11.0 Voltage Identification Definition (Sheet 1 of 3) VID 7 VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 VCC_MAX 0 0 0 0 0 0 0 0 OFF 0 0 0 0 0 0 0 1 OFF 0 0 0 0 0 0 1 0 1.60000 0 0 0 0 0 0 1 1 1.59375 0 0 0 0
  • Intel BV80605001914AG | Data Sheet - Page 64
    Electrical Specifications Table 7-1. VRD 11.1/11.0 Voltage Identification Definition (Sheet 2 of 3) VID 7 VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 1 0 1 0 0 1 1 0 0.57500 1 0 1 0 0 1 1 1 0.56875 1 0 1 0 1 0 0 0 0.56250 1 0 1 0 1 0 0 1 0.55625 64 Datasheet, Volume 1
  • Intel BV80605001914AG | Data Sheet - Page 65
    the maximum platform capability to the processor. 2. 2009A processors have thermal requirements that are equivalent to those of the Intel® Core™2 Duo E8000 processor series. Refer to the appropriate processor Thermal and Mechanical Specifications and Design Guidelines for additional information
  • Intel BV80605001914AG | Data Sheet - Page 66
    in component malfunction or incompatibility with future processors. See Chapter 8 for a land listing of the processor and the location of all reserved signals Table 7-3. The buffer type indicates which signaling technology and specifications apply to the signals. All the differential signals, and
  • Intel BV80605001914AG | Data Sheet - Page 67
    Electrical Specifications Table 7-3. Signal Groups (Sheet 1 of 2)1 Signal Group System Reference Clock Alpha Group Differential (a) Differential (b) DDR3 Reference Clocks2 Differential (c) DDR3 Command Signals2 Single Ended (d) DDR3 Data
  • Intel BV80605001914AG | Data Sheet - Page 68
    SB refer to DDR3 Channel A and DDR3 Channel B. 3. These signals are only used on processors and platforms that support ECC DIMMs. 4. These signals will not be actively used on the Intel Xeon processor 3400 series. All Control Sideband Asynchronous signals are required to be asserted/de-asserted for
  • Intel BV80605001914AG | Data Sheet - Page 69
    Specifications 7.7 Test Access Port (TAP) Connection Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, Intel recommends the processor Processor Absolute Minimum and Maximum Ratings Symbol VCC VTT VDDQ VCCPLL TSTORAGE Parameter Processor Core voltage
  • Intel BV80605001914AG | Data Sheet - Page 70
    . Voltage and Current Specifications Table 7-5. Processor Core Active and Idle Mode DC Voltage and Current Specifications Symbol VID VCC VCC,BOOT Parameter VID Range VCC for processor core Default VCC voltage for initial power up Processor Number For Intel Xeon processor 3400 series with 95
  • Intel BV80605001914AG | Data Sheet - Page 71
    for DDR3 1.425 1.5 1.575 V VCCPLL PLL supply voltage (DC + AC specification) 1.71 1.8 1.89 V Intel Xeon processor 3400 series ITT with 95 W TDP: Current for the memory controller and Shared - - Cache 35 A Intel Xeon processor 3400 series ITT with 45 W TDP: Current for the memory
  • Intel BV80605001914AG | Data Sheet - Page 72
    Electrical Specifications Table 7-7. VCC Static and Transient Tolerance Voltage Deviation from VID Setting 1, 2, 3 ICC (A) VCC_Max (V) 1. regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and VSS_SENSE lands. Refer to the Voltage Regulator Down (
  • Intel BV80605001914AG | Data Sheet - Page 73
    Electrical Specifications Figure 7-1. VCC Static and Transient Tolerance Loadlines 0 VID - 0.000 VID - 0.013 VID - 0.025 VID - 0.038 10 20 30 Icc [A] 40 50 60 VID - 0.050 VID - 0.
  • Intel BV80605001914AG | Data Sheet - Page 74
    may experience excursions above VDDQ. However, input signal drivers must comply with the signal quality specifications. 5. This is the pull down driver resistance. 6. RVTT_TERM is the termination on the DIMM and is not controlled by the processor. 7. COMP resistance must be provided on the system
  • Intel BV80605001914AG | Data Sheet - Page 75
    , all specifications in this table apply to all processor frequencies. 2. 3. The For VVITNT referred between 0toVinanthdeVseTT.spMeecaifsicuarteidonwshreenfetrhsetodriinvsetranistatrniestoautsedV.TT. 4. VIH and VOH may experience excursions above VTT. However, input signal drivers must comply
  • Intel BV80605001914AG | Data Sheet - Page 76
    20 100 120 120 60 120 1.2 1.2 150 50.5 50.5 50.5 757.5 Units V mV mV V V mV Notes1 3 1,2,6 1,2 1,10 1,10 1,8,9 1 1 1,1 1,7 4,5 4,5 4,5 4,5 Notes: 1. Refer to the PCI Express Base Specification for more details. 2. aVtTXle-AaCs-tCM1-0P^P 6anUdI.VTX-AC-CM-P are defined in the PCI Express Base
  • Intel BV80605001914AG | Data Sheet - Page 77
    for external devices to read the DTS temperature for thermal management and fan speed control. For the PECI command set supported by the processor, refer to the appropriate processor Thermal and Mechanical Specifications and Design Guidelines for additional information (see Section 1.7). 7.10.1 DC
  • Intel BV80605001914AG | Data Sheet - Page 78
    Electrical Specifications 7.10.2 Input Device Hysteresis The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 7-2 as a guide for input buffer design. Figure 7-2. Input Device Hysteresis VTTD Maximum VP Minimum VP Maximum
  • Intel BV80605001914AG | Data Sheet - Page 79
    8-1 lists the signals that are not used by the Intel Xeon processor 3400 series. Table 8-1. Signals Not Used by the Intel® Xeon® Processor 3400 Series Interface Intel Flexible Display Interface Integrated Graphics Core Power Memory Signals Not Used FDI_FSYNC[1:0] FDI_LSYNC[1:0] FDI_INT FDI_TX
  • Intel BV80605001914AG | Data Sheet - Page 80
    Processor Land and Signal Information Figure 8-1. Socket Pinmap (Top View, Upper-Left Quadrant) 40 39 38 37 36 35 34 33 32 31 30 29 28
  • Intel BV80605001914AG | Data Sheet - Page 81
    Processor Land and Signal Information Figure 8-2. Socket Pinmap (Top View, Upper-Right Quadrant) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 VDDQ VDDQ
  • Intel BV80605001914AG | Data Sheet - Page 82
    Processor Land and Signal Information Figure 8-3. Socket Pinmap (Top View, Lower-Left Quadrant) Y VTT VTT VTT VTT VTT VTT W VSS VSS VSS VSS VSS VSS V VTT
  • Intel BV80605001914AG | Data Sheet - Page 83
    Processor Land and Signal Information Figure 8-4. Socket Pinmap (Top View, Lower-Right Quadrant) VSS BCLK#[1] FDI_TX[7] FDI_TX#[7] FDI_TX[6] FDI_TX#[6] Y VTT VTT FDI_TX[3] FDI_TX#[3] FDI_TX[4] FDI_TX#[4] DMI_RX[3]
  • Intel BV80605001914AG | Data Sheet - Page 84
    Analog I COMP3 C11 Analog I DBR# AL40 O SA_DIMM_VREFDQ AF3 Analog O SB_DIMM_VREFDQ AG3 Analog O DMI_RX[0] R1 DMI I DMI_RX[1] U3 DMI I Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. DMI_RX[2] U1 DMI I DMI_RX[3] W3 DMI I DMI_RX#[0] T1 DMI
  • Intel BV80605001914AG | Data Sheet - Page 85
    Express I B5 PCI Express I C4 PCI Express I D3 PCI Express I E2 PCI Express I F1 PCI Express I G2 PCI Express I C7 PCI Express O Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. PEG_TX[1] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX
  • Intel BV80605001914AG | Data Sheet - Page 86
    AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM25 AM26 AM27 AM28 AM29 AM30 L12 M12 A4 AU40 AV1 AV39 AW2 AW38 AY3 Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. RSVD_NCTF RSVD_NCTF RSVD_NCTF RSVD_NCTF RSVD_TP SA_BS[0] SA_BS[1] SA_BS[2] SA_CAS# SA_CK[0] SA_CK[1] SA_CK
  • Intel BV80605001914AG | Data Sheet - Page 87
    AW33 DDR3 I/O AW35 DDR3 I/O AY35 DDR3 I/O AH2 DDR3 I/O AV37 DDR3 I/O AU37 DDR3 I/O AY34 DDR3 I/O AW34 DDR3 I/O AV36 DDR3 I/O Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. SA_DQ[55] AW37 DDR3 I/O SA_DQ[56] AT39 DDR3 I/O SA_DQ[57] AT40
  • Intel BV80605001914AG | Data Sheet - Page 88
    DDR3 O AV26 DDR3 O AV29 DDR3 O AM23 DDR3 O AM24 DDR3 O AL24 DDR3 O AK24 DDR3 O AE4 DDR3 O AH4 DDR3 O AM7 DDR3 O Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7] SB_DQ[0] SB_DQ[1] SB_DQ[10] SB_DQ[11
  • Intel BV80605001914AG | Data Sheet - Page 89
    SB_DQS#[5] AR32 DDR3 I/O SB_DQS#[6] AR37 DDR3 I/O SB_DQS#[7] AM36 DDR3 I/O SB_DQS#[8] AR13 DDR3 I/O SB_ECC_CB[0] AR12 DDR3 I/O Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. SB_ECC_CB[1] SB_ECC_CB[2] SB_ECC_CB[3] SB_ECC_CB[4] SB_ECC_CB[5] SB_ECC_CB
  • Intel BV80605001914AG | Data Sheet - Page 90
    Signal Information Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VAXG VAXG PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VAXG VAXG VAXG VAXG VAXG VAXG_SENSE VCC VCC
  • Intel BV80605001914AG | Data Sheet - Page 91
    Signal Information Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VCC VCC VCC PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VCC VCC VCC VCC VCC VCC VCC VCC VCC
  • Intel BV80605001914AG | Data Sheet - Page 92
    Signal Information Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VCC VCC PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VCC P37 PWR VCC P38 PWR VCC P39
  • Intel BV80605001914AG | Data Sheet - Page 93
    Land and Signal Information Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VID[5]/CSC GND VSS AJ16 GND VSS AJ18 GND VSS AJ20 GND VSS AJ22 GND VSS AJ24 GND Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VSS VSS VSS VSS VSS
  • Intel BV80605001914AG | Data Sheet - Page 94
    Signal Information Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VSS VSS VSS GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VSS VSS VSS VSS VSS VSS VSS VSS VSS
  • Intel BV80605001914AG | Data Sheet - Page 95
    Signal Information Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VSS VSS VSS GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VSS VSS VSS VSS VSS VSS VSS VSS VSS
  • Intel BV80605001914AG | Data Sheet - Page 96
    Signal Information Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VSS VSS PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VTT AD40 PWR VTT AE33 PWR VTT AE34
  • Intel BV80605001914AG | Data Sheet - Page 97
    Signal Information Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT_SELECT VTT_SENSE VTTPWRGOOD V7
  • Intel BV80605001914AG | Data Sheet - Page 98
    Processor Land and Signal Information 98 Datasheet, Volume 1
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Document Number: 322371-003
Intel
®
Xeon
®
Processor 3400 Series
Datasheet – Volume 1
June 2010