Intel BX80562Q6600 Specification Update
Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor Manual
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- Intel BX80562Q6600 | Specification Update - Page 1
and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - on 65 nm Process in the 775-land LGA Package supporting Intel® 64Φ Architecture and Intel® Virtualization Technology± December 2010 Notice: The Intel® Core™2 Extreme quad-core processor and Intel® Core™2 quad processor may - Intel BX80562Q6600 | Specification Update - Page 2
Disable Bit functionality. The Intel® Core™2 Extreme quad-core processor and Intel® Core™2 Quad processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel® 64 - Intel BX80562Q6600 | Specification Update - Page 3
Information ...18 Component Identification Information 19 Errata ...21 Specification Changes ...67 Specification Clarifications 68 Documentation Changes ...69 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 3 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 4
• Added Specification Clarification AK1 • Updated Erratum AK14, AK25 and AK26 • Added Errata AK106 and AK107 • Included G0 stepping information (updated summary tables of change and updated processor identification information) • Added Errata AK108 to AK111 • Added Intel® Core™2 Quad processor Q6600 - Intel BX80562Q6600 | Specification Update - Page 5
Oct 2007 Nov 2007 Dec 2007 Jan 2008 Feb 13th 2008 May 2008 March 2009 May 2009 July 2009 March 16, 2010 December 8th, 2010 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 5 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 6
® 64 and IA-32 Architecture Software Developer's Manual Volume 3B: System Programming Guide Document Location http://www.intel.com/products/ processor/manuals/index.htm 6 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification - Intel BX80562Q6600 | Specification Update - Page 7
from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, etc.). § Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 7 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 8
fixed. There are no plans to fix this erratum. Row Shaded: This item is either new or modified from the previous version of the document. 8 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 9
process Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65nm process Dual-Core Intel® Xeon® processor LV Dual-Core Intel® Xeon® processor 5100 series Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 9 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 10
-Check Architecture (MCA) on Single-bit L2 ECC Errors May be Incorrect VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (LER) MSR 10 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 11
Instructions Greater than 15 Bytes May be Preempted Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced Before Higher Priority Interrupts The Processor Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 11 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 12
FXSAVE Concurrent Multi-processor Writes to Non-dirty Page May Result in Unpredictable Behavior Performance Monitor IDLE_DURING_DIV (18h) Count May Not be Accurate 12 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 13
Fail when VMCS is Programmed to Cause VM Exit to Return to a Different Mode IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 13 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 14
Program Order Performance Monitor SSE Retired Instructions May Return Incorrect Values Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame 14 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 15
Enabled May Result in Old/Out-ofdate LBR Information Overlap of an Intel® VT APIC Access Page in a Guest with the DS Save Area May Lead to Unpredictable Behavior Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 15 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 16
Summary Tables of Changes NO B3 G0 AK109 X AK110 X X AK111 X Bit Address Size in 64-bit Mode A 64-bit Register IP-relative Instruction May Return Unexpected Results 16 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification - Intel BX80562Q6600 | Specification Update - Page 17
are no Specification Clarifications in this Specification Update revision. Number DOCUMENTATION CHANGES There are no Documentation Changes in this Specification Update revision. § Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 17 Intel® Core™2 Quad Processor Q6000Δ Sequence - Intel BX80562Q6600 | Specification Update - Page 18
/05B [FPO] e4 ATPO S/N Figure 2. Intel® Core™2 quad processor Package INTEL M ©'05 Q6600 INTEL® CORE™2 QUAD SLxxx [COO] 2.40GHZ/8M/1066/05B [FPO] e4 ATPO S/N § 18 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 19
Q6600 2.4 GHz / 1066 MHz 775-land LGA 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 15 NOTES: 1. These processors support the 775_VR_CONFIG_05B specifications 2. These processors support the 775_VR_CONFIG_05A specifications 3. These parts support Intel® 64 Intel® Core™2 Extreme Quad-Core Processor QX6000 - Intel BX80562Q6600 | Specification Update - Page 20
. 13.These parts have Extended HALT (C1E) power of 50W 14.These parts have Extended HALT (C1E) power of 37W 15.These parts have Extended HALT (C1E) power of 24W § 20 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 21
Under some scenarios, the address reported may be incorrect. Implication: Software should not rely on the value reported in MCi_ADDR, for Single-bit L2 ECC errors. Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 21 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 22
saved upon execution of the SYSCALL instruction). Due to this erratum, the RFLAGS.RF bit will be unconditionally cleared after execution of the SYSRET instruction. 22 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 23
systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel has not observed this erratum with any commercially available software. Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 23 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 24
respective thermal interrupt enable bit. When programming DTS value, the previous DTS threshold may be crossed. This will generate an unexpected thermal interrupt. 24 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 25
instructions are not counted. • HLT and MWAIT instructions are not counted. The following instructions, if executed during HLT or MWAIT events, are also not counted: Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 25 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification - Intel BX80562Q6600 | Specification Update - Page 26
references a large page. A20M# is normally only used with the first megabyte of memory. Status: For the steppings affected, see the Summary Tables of Changes. 26 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 27
instructions after the floatingpoint operation which causes the precision exception: • FST m32real • FST m64real • FSTP m32real • FSTP m64real • FSTP m80real • FIST m16int Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 27 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification - Intel BX80562Q6600 | Specification Update - Page 28
to non- canonical address 0000800000000000), under some circumstances the code fetch will be converted to a canonical fetch at address ffff800000000000. 28 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 29
detected. Workaround: No workaround is necessary due to the PECI error handling protocol. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 29 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 30
and by ensuring that all code is written such that a code segment limit violation cannot occur as a part of reading from side-effect memory. 30 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 31
as interrupts) will cause the (E)CX registers to be increment by a value that corresponds to 64K bytes for 16 bit address size and 4G bytes for 32 bit address size. Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 31 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 32
through BTMs or BTSs may be incorrect during this transition Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 32 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 33
or a partial memory state restore of the FXRSTOR image may occur if a memory address exceeds the 64KB limit while the processor is operating in 16-bit mode or if a Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 33 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 34
address (alignment - Intel BX80562Q6600 | Specification Update - Page 35
instructions may not be executed when Alignment Check is enabled. Implication: PREFETCH instructions may not perform the data prefetch if Alignment Check is enabled. Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 35 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification - Intel BX80562Q6600 | Specification Update - Page 36
a value higher or lower than the actual number of events. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 36 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 37
) fault is generated after all higher priority Interrupts and exceptions are serviced. Due to this erratum, if RSM (Resume from System Management Mode) returns to Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 37 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 38
after MOV SS/POP SS if this instruction is followed by an instruction that signals a floating point exception rather than a MOV [r/e]SP, [r/e]BP instruction. This 38 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 39
has not been configured to generate a synchronous SMI for the recorded I/O port address. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 39 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 40
observed this erratum with any commercially available system. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 40 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 41
now always be 8 bytes, as opposed to the original data size and there may be a memory ordering violation. • WT there may be a memory ordering violation. Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 41 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 42
register would have held had the instruction completed without fault. This can occur even if the fault causes a VM exit or if its delivery causes a nested fault. 42 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 43
and logs the event (IA32_THERM_STATUS MSR (019Ch) bits [9,7]). Due to this erratum, if the DTS reaches an invalid temperature (as indicated IA32_THERM_STATUS MSR Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 43 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 44
following specific cases: • FADD and FMUL instructions with a NaN(Not a Number) operand and a memory operand • FDIV instruction with zero operand value in memory 44 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 45
delayed by one PEBS event. Implication: Debug Store Interrupt Service Routines may observe delay of PMI occurrence by one PEBS event. Workaround: None identified. Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 45 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 46
will not be used. Workaround: Use an interrupt task gate for the machine check handler. Status: For the steppings affected, see the Summary Tables of Changes. 46 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 47
-from instruction address may get corrupted for software interrupts. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 47 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification - Intel BX80562Q6600 | Specification Update - Page 48
same address the first load may get the data from external memory or L2 written by another core, while the second load will get the data straight from the WT Store. 48 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 49
as follows: • #DB is signaled before the pending higher priority #MF (Interrupt 16) • #DB is generated twice on the same instruction Workaround: None identified. Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 49 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 50
observed this erratum on any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 50 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 51
-executable page can be placed after the limit of the code segment to prevent this erratum. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 51 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 52
Decoded Instructions Problem: MACRO_INSTS.DECODED performance monitoring counter (Event 0AAH, Umask 01H) counts the number of macro instructions decoded, but not 52 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 53
of PMULUDQ instructions, while the counter is active. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 53 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 54
: Memory ordering may be violated between WC and WP stores. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 54 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 55
the TSC and the CPU_CLK_UNHALTED.REF performance monitoring event count (this can be done by measuring simultaneously their counted value while executing code) Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 55 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 56
steppings affected, see the Summary Tables of Changes. AK102. Performance Monitoring Event BR_INST_RETIRED May Count CPUID Instructions as Branches Problem range. 56 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 57
old/out-of-date LBR information that does not describe the last few branches before the PEBS sample that triggered the PMI. Workaround: None identified. Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 57 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 58
above. Workaround: It is possible for BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. 58 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 59
of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 59 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 60
of a WB (write back) memory type to a cache line previously written by a preceding fast string/FXSAVE instruction may be observed before string/FXSAVE stores. 60 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 61
a cacheable memory type and WC (write combining) may cause the processor to perform incorrect operations leading to memory ordering violations for WC operations. Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 61 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 62
for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AK120. Problem: NMIs May Not Be Blocked by a VM-Entry Failure The Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2 specifies that, following a VM - Intel BX80562Q6600 | Specification Update - Page 63
fault causes a VM exit, incorrect data may be saved into the VMCS. Specifically, information about the software interrupt may not be reported in the IDT-vectoring Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 63 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 64
set. Implication: Software may not operate properly if it relies on the processor to deliver page faults when reserved bits are set in paging-structure entries. 64 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 65
-bit mode and the memory access wraps a 4-Gbyte boundary and the FP environment is subsequently saved, the value contained in the FP Data Operand Pointer may be incorrect. Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 65 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification - Intel BX80562Q6600 | Specification Update - Page 66
. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. § 66 Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update - Intel BX80562Q6600 | Specification Update - Page 67
: • Intel® Core™2 Extreme Quad-Core Processor QX6700Δ and Intel® Core™2 Quad Processor Q6000Δ Sequence Datasheet • Intel® Core™2 Extreme Quad-Core Processor QX6800 Datasheet • Intel® 64 and IA-32 Architectures Software Developer's Manual volumes 1, 2A, 2B, 3A, and 3B All Specification Changes will - Intel BX80562Q6600 | Specification Update - Page 68
: • Intel® Core™2 Extreme Quad-Core Processor QX6700Δ and Intel® Core™2 Quad Processor Q6000Δ Sequence Datasheet • Intel® Core™2 Extreme Quad-Core Processor QX6800 Datasheet • Intel® 64 and IA-32 Architectures Software Developer's Manual volumes 1, 2A, 2B, 3A, and 3B All Specification Clarifications - Intel BX80562Q6600 | Specification Update - Page 69
Developer's manual documentation changes. Follow the link below to become familiar with this file. http://www.intel.com/products/processor/manuals/index.htm § Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and 69 Intel® Core™2 Quad Processor Q6000Δ Sequence Specification Update
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Intel
®
Core™2 Extreme Quad-
Core Processor QX6000
Δ
Sequence and Intel
®
Core™2
Quad Processor Q6000
Δ
Sequence
Specification Update
—
on 65 nm Process in the 775-land LGA Package supporting
Intel
®
64
Φ
Architecture and Intel
®
Virtualization Technology±
December 2010
Document Number:
315593-027
Notice:
The Intel
®
Core™2 Extreme quad-core processor and Intel
®
Core™2 quad
processor may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are
documented in this Specification Update.