Intel BX80569Q9550 Data Sheet

Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Manual

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  • Intel BX80569Q9550 | Data Sheet - Page 1
    Fixed Frequency with 10 MB L3 Cache 9310 Intel® Itanium® Processor Eight-Core 2.53 GHz with 32 MB LLC Cache 9560 Intel® Itanium® Processor Four-Core 2.40 GHz with 32 MB LLC Cache 9550 Intel® Itanium® Processor Eight-Core 2.13 GHz with 24 MB LLC Cache 9540 Intel® Itanium® Processor Four-Core 1.73 GHz
  • Intel BX80569Q9550 | Data Sheet - Page 2
    PRODUCT OR ANY OF ITS PARTS. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall
  • Intel BX80569Q9550 | Data Sheet - Page 3
    Voltage Identification for the Intel® Itanium® Processor 9500 Series 59 2.8 Cache Voltage Identification (Intel® Itanium® Processor 9300 Series only 62 2.9 RSVD, Unused, and DEBUG Pins 63 2.10 Mixing Processors 64 2.11 Supported Power-up Voltage Sequence 64 2.11.1 Supported Power-up Voltage
  • Intel BX80569Q9550 | Data Sheet - Page 4
    Data 152 6.4.4 Processor Uncore Data 153 6.4.5 Cache Data 154 6.4.6 Package Data 155 6.4.7 Part Number Data 155 6.4.8 Thermal Reference Data 155 6.4.9 Feature Data 156 6.4.10 Other Data 157 6.4.11 Checksums 157 7 Signal Definitions 159 4 Intel® Itanium® Processor 9300 Series and 9500
  • Intel BX80569Q9550 | Data Sheet - Page 5
    Power-up Voltage Sequence Timing Requirements for the Intel® Itanium® Processor 9300 Series 66 2-18 Supported Power-up Sequence Timing Requirements for Intel® Itanium® Processor 9500 Series 67 2-19 Supported Power-down Voltage Sequence Timing Requirements 69 2-20 RESET_N and SKITID Timing
  • Intel BX80569Q9550 | Data Sheet - Page 6
    ® Processor 9300 Series 40 FMB 130W Current Specifications for the Intel® Itanium® Processor 9300 Series .......41 2-17 FMB 155W/185W Current Specifications for the Intel® Itanium® Processor 9300 Series 42 2-18 FMB Voltage Specifications for the Intel® Itanium® Processor 9500 Series 43 2-19 FMB
  • Intel BX80569Q9550 | Data Sheet - Page 7
    9300 Series 134 Thermal Sensor Accuracy Distribution for the Intel® Itanium® Processor 9500 Series 135 Thermal Specification for the Intel® Itanium® Processor 9300 Series 139 Thermal Specification for the Intel® Itanium® Processor 9500 Series Processor ....... 139 Storage Condition Ratings
  • Intel BX80569Q9550 | Data Sheet - Page 8
    Revision History Document Number 322821 322821 Revision Number -002 -001 Description • Initial release of the 9300/9500 document. • Initial release of the document. § Date November 2012 February 2010 8 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 9
    exposing available Instruction Level Parallelism support a range of computing needs and configurations from a 2-way to large SMP servers (although OEM field upgrade methodologies vary). This document provides the electrical, mechanical and thermal specifications that must be met when using the Intel
  • Intel BX80569Q9550 | Data Sheet - Page 10
    Introduction 10 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 11
    L3 Cache 9320 Intel® Itanium® Processor Dual-Core 1.60 GHz Fixed Frequency with 10 MB L3 Cache 9310 Product Features  Quad Core - Four complete 64-bit processing cores on one processor. - Includes Dynamic Domain Partitioning.  Advanced EPIC (Explicitly Parallel Instruction Computing) Architecture
  • Intel BX80569Q9550 | Data Sheet - Page 12
    of all architectural state to support hardware multithreading, thus enabling greater throughput. Three levels of on-die cache minimize overall memory latency. It interfaces with the Ararat "1" Voltage Regulator Module, which used exclusively with the Intel® Itanium® Processor 9300 Series. 12
  • Intel BX80569Q9550 | Data Sheet - Page 13
    24 MB LLC Cache 9540 Intel® Itanium® Processor Four-Core 1.73 GHz with 20 MB LLC Cache 9520 Product Features  Eight Core - Eight complete 64-bit processing cores on one processor, with two threads per core. - Each core provides in-order issue and execution of up to twelve instructions per cycle
  • Intel BX80569Q9550 | Data Sheet - Page 14
    recovery-support on all used by the processor to temporarily allocate more resources to a thread). Advanced Explicitly Parallel Instruction Computing (EPIC) is enhanced on the Intel cache MLD that comprise the MLC. The Intel® Itanium® Processor 9500 Series offers a new RAS feature: Intel® Instruction
  • Intel BX80569Q9550 | Data Sheet - Page 15
    . The Caching Agent, Home Agent, and Intel QuickPath Interconnects are connected via a 12-port Crossbar Router, each port supporting the Intel QuickPath Interconnect protocol. Figure 1-1 shows the Intel® Itanium® Processor 9300 Series block diagram. The Intel QPI viral and poison fields are used to
  • Intel BX80569Q9550 | Data Sheet - Page 16
    Intel® QPI Intel® QPI Intel® Itanium® Processor 9500 Series Overview The Intel® Itanium® Processor 9500 Series is an eight core architecture. It supports up to eight cores, each with its own First Level Cache (FLC) and Mid Level Cache (MLC), both of which are split into instruction and data caches
  • Intel BX80569Q9550 | Data Sheet - Page 17
    block of data is not reliable. Intel® Itanium® Processor 9500 Series PAL's Demand Based Switching (DBS) support includes implementations of Power/Performance states (P-states) and Halt states (Cstates). For the PAL Halt state interface and architected specifications of the PAL Pstate interface, see
  • Intel BX80569Q9550 | Data Sheet - Page 18
    polices of the protection key cache. Before a memory access (including specific documentation for further information on the number of protection key registers and protection key bits implemented on the processor. Figure 1-3. Intel® Itanium® Processor 9500 Series Firmware Diagram 18 Intel
  • Intel BX80569Q9550 | Data Sheet - Page 19
    Directory Cache Intel® Virtualization Technology (Intel® VT) Hot add/hot removal at Intel QPI link and DIMM memory interface Hot add CPU Hot add memory Hot remove/hot replace memory Memory sparing technique Memory scrubbing Memory mirroring Supported 50 physical/64 virtual four caching agents
  • Intel BX80569Q9550 | Data Sheet - Page 20
    , 155W, 185W Notes: 1. OEM responsible for specifying platform-specific retraining interval. 2. Electrical isolation only, no physical add/remove supported. 3. Assume spare is installed. Intel® Itanium® Processor 9500 Series Supported Supported Supported Supported Supported Supported 130W and 170W
  • Intel BX80569Q9550 | Data Sheet - Page 21
    ® Architecture Software Developer's Manual, Volume 2: System Architecture Intel® Itanium® Architecture Software Developer's Manual, Volume 3: Instruction Set Reference Intel® Itanium® Architecture Software Developer's Manual, Volume 4: IA-32 Instruction Set Reference Intel® Itanium® 9300 Series
  • Intel BX80569Q9550 | Data Sheet - Page 22
    Introduction 22 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 23
    Intel® QuickPath Interconnect (Intel® QPI) and Intel® Scalable Memory Interconnect (Intel® SMI) signals use differential signaling. The Intel® available revision of the Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series Platform Design Guide. Figure 2-1 illustrates the
  • Intel BX80569Q9550 | Data Sheet - Page 24
    listed in Table 2-2. The buffer type indicates which signaling technology and specifications apply to the signals. Table 2-2. Signal Groups (Sheet 1 of System Reference Clock Differential CMOS In Differential Pair Intel® QuickPath Interconnect Signal Groups Differential Input Differential
  • Intel BX80569Q9550 | Data Sheet - Page 25
    Electrical Specifications Table 2-2. Signal Groups (Sheet 2 of 3) Signal Group Buffer Type Signals 1, 2, 3 Single Series) Single-ended CMOS Output VID_VCCCORE[6:0], VID_VCCCACHE[5:0], VID_VCCUNCORE[6:0] SVID Port4 (Intel® Itanium® Processor 9500 Series) Single-ended GTL Output GTL I/O
  • Intel BX80569Q9550 | Data Sheet - Page 26
    Electrical Specifications Table 2-2. Signal Groups (Sheet 3 of 3) Signal Group Buffer Type Signals 1, 2, 3 Debug GTL I/O Single-ended GTL Input GTL Output Power Supplies Core Uncore Cache (Intel® Itanium® Processor 9300 Series) Analog I/O Stand-by VCC33_SM Pins PIROM Input I/O Input
  • Intel BX80569Q9550 | Data Sheet - Page 27
    Electrical Specifications Table 2-3. Intel® QuickPath Interconnect/Intel® Scalable Memory Interconnect Reference Clock Specifications (Sheet 2 of 2) Symbol the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing. See Figure 2-4. 5.
  • Intel BX80569Q9550 | Data Sheet - Page 28
    100mV VRefclk-diff-ih =- 150mV REFCLK diff TStable TStable 2.4 . 2.4.1 Intel® QuickPath Interconnect and Intel® SMI Signaling Specifications Intel® Itanium® Processor 9300 Series Intel® QuickPath Interconnect and Intel® SMI Specifications for 4.8 GT/s The applicability of this section applies to
  • Intel BX80569Q9550 | Data Sheet - Page 29
    Electrical Specifications Table 2-4. Intel® Itanium® Processor 9300 Series Clock Frequency Table Intel® QuickPath Interconnect Forwarded Clock Frequency 33.33 MHz 2.40 GHz Intel® QuickPath Interconnect Data Transfer Rate 66.66 MT/s (see note 1) 4.8 GT/s Notes: 1. This speed is the 1/4 SysClk
  • Intel BX80569Q9550 | Data Sheet - Page 30
    entire signalling voltage range shall not exceed ±5 ohms. 5. Requires Matlab script. 6. Refer to Intel® QuickPath Interconnect (Intel® QPI) - Electrical Specifications for calculation of this value. Note that UI to UI. definition is used herein, where the value of UI-UI DCD = 2*UI DCD. 7. See Figure
  • Intel BX80569Q9550 | Data Sheet - Page 31
    Intel® Itanium® Processor 9300 Series Receiver Parameter Values for Intel® QuickPath Interconnect and Intel® SMI Channels @ 4.8 GT (Sheet 2 of 2) Parameter Min Nom Max Units Notes Minimum eye width at pin for clk and data 0.6 Bit Link BER is the dominant spec of which eye dimensions are only
  • Intel BX80569Q9550 | Data Sheet - Page 32
    Figure 2-7. TX Return Loss Electrical Specifications Figure 2-8. RX Return Loss 2.4.2 Intel® Itanium® Processor 9500 Series Requirements for Intel® QuickPath Interconnect for 4.8 and 6.4 GT/s The applicability of this section applies to Intel® Itanium® Processor 9500 Series. This section
  • Intel BX80569Q9550 | Data Sheet - Page 33
    captured in Table 2-10. Table 2-8. Intel® Itanium® Processor 9500 Series Link Speed Independent Specifications (Sheet 1 of 2) Symbol UIavg mask voltage and timing spec needs to be validated 1,000,000 Single ended DC 4k impedance to GND for either D+ or D- of any data bit at Tx Single ended
  • Intel BX80569Q9550 | Data Sheet - Page 34
    Specifications Table 2-8. Intel® Itanium® Processor 9500 Series Link Speed Independent Specifications vs for any data bit at Rx Bit Error Rate per lane Used during initialization. It is the state of "OFF" condition for the receiver when only the minimum termination is connected. Table 2-9. Intel
  • Intel BX80569Q9550 | Data Sheet - Page 35
    Specifications Table 2-9. Intel® Itanium® Processor 9500 Series Transmitter and Receiver Parameter Values for Intel CPU to CPU or CPU to spec then we can allow the transmitter AC CM noise to pass. Table 2-10. Intel® Itanium® Processor 9500 Series Transmitter and Receiver Parameter Values for Intel
  • Intel BX80569Q9550 | Data Sheet - Page 36
    Specifications Table 2-10. Intel® Itanium® Processor 9500 Series Transmitter and Receiver Parameter Values for Intel mV Notes: 1. 1300 mVpp swing is recommended when CPU to CPU or CPU to IOH length is within 2" of PDG max components meets the RX AC CM spec then we can allow the transmitter
  • Intel BX80569Q9550 | Data Sheet - Page 37
    specification for transmit and receive are captured in Table 2-12. Table 2-11. Intel® Itanium® Processor 9500 Series Transmitter and Receiver Parameter Values for Intel 25*VTx-diff-pp-pin) bias point Transmitter differential swing using a CLK like pattern Transmitter output DC common mode, defined
  • Intel BX80569Q9550 | Data Sheet - Page 38
    . The contribution of cross-talk may be significant and should be done using the same setup at Tx and compared against the expectations of full link signaling. Note that there may be cases when one of Dj and Rj specs is met and another violated in which case the signaling analysis should
  • Intel BX80569Q9550 | Data Sheet - Page 39
    2.6.4. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor. 2.6 Processor DC Specifications Table 2-15 through Table 2-35 list the DC specifications for the Intel® Itanium® Processor 9300 Series and 9500 Series and are valid only while meeting
  • Intel BX80569Q9550 | Data Sheet - Page 40
    specification values applied to the 130 W and 170 W SKUs for the Intel® Itanium® Processor 9500 Series. Current specifications cache supply voltage VID step size during transition Total allowable DC load line shift from VID steps analog supply voltage (Total = DC spec + AC tolerance) 3.3 V supply
  • Intel BX80569Q9550 | Data Sheet - Page 41
    /or the scope at 1 MHz BW limit (capture waveform B, channel 2). Step 2 = calculate A-B (use scope Math function: subtract channel 1 - channel 2). Table 2-16. FMB 130W Current Specifications for the Intel® Itanium® Processor 9300 Series Symbol Parameter Max Units Notes ICC_CORE ICC_CORE_TDC
  • Intel BX80569Q9550 | Data Sheet - Page 42
    Specifications for the Intel® Itanium® Processor 9300 Series Symbol Parameter Max Units Notes ICC_CORE ICC_CORE_TDC ICC_CORE_STEP dICC_CORE/dt ICC_UNCORE ICC_UNCORE_TDC ICC_UNCORE_STEP dICC_UNCORE/dt ICC_IO ICC_Analog ICC33_SM ICC for core Thermal Design Current for Core Max Load step Guide
  • Intel BX80569Q9550 | Data Sheet - Page 43
    . See the Ararat II Voltage Regulator Module Design Guide for more information. 3. Uncore and Core voltage and Current Rating are at the Package Pad. 4. The voltage specification requirements are measured across the VCCCORESENSE and VSSCORESENSE pins using an oscilloscope set to a 100 MHz bandwidth
  • Intel BX80569Q9550 | Data Sheet - Page 44
    Step 2 = calculate A-B (use scope Math function: subtract channel 1 - channel 2). Table 2-19. FMB 170W and 130W Current Specifications for the Intel® the processor. Please see the Ararat II Voltage Regulator Module Design Guide for further details. The processor is capable of drawing ICC_CORE_TDC
  • Intel BX80569Q9550 | Data Sheet - Page 45
    Electrical Specifications Table 2-20. SVeCCriUeNsCORE Static and Transient Tolerance for Intel® Itanium® Processor 9300 Uncore Current (A) Voltage Deviation from VID Setting pins. Refer to the Ararat Voltage Regulator Module Design Guide for socket load line guidelines and VR implementation.
  • Intel BX80569Q9550 | Data Sheet - Page 46
    Electrical Specifications 2.6.3.2 Core Static and Transient Tolerances Table 2-21 and Figure 2-11 specify static and transient tolerances for the core outputs. Table 2-21. VSeCCriCeOsR(ESShteaettic1aonfd2T)ransient Tolerance for Intel® Itanium® Processor 9300 Core Current (A) Voltage Deviation
  • Intel BX80569Q9550 | Data Sheet - Page 47
    Specifications Table 2-21. SVeCCriCeOsR(ESShteaettic2aonfd2T)ransient Tolerance for Intel Ararat Voltage Regulator Module Design Guide for socket load line guidelines Cache Static and Transient Tolerances Table 2-22 and Figure 2-12 specify static and transient tolerances for the cache outputs. Intel
  • Intel BX80569Q9550 | Data Sheet - Page 48
    Electrical Specifications Table 2-22. VSeCCriCeAsCHE Static and Transient Tolerance for Intel® Itanium® Processor 9300 Cache Current (A) Voltage Deviation from the Ararat Voltage Regulator Module Design Guide for sboecktaekt elonafdrolminepgroucideesslionresVCaCndanVdRVSS pins. implementation.
  • Intel BX80569Q9550 | Data Sheet - Page 49
    Electrical Specifications 2.6.4 Intel® Itanium® Processor 9500 Series Uncore and Core Tolerances 2.6.4.1 be taken from processor VCC and VSS pins. Refer to the Ararat II Voltage Regulator Module Design Guide for socket load line guidelines and VR implementation. 4. VDC(max)=VID-Rll*ICC+15 mV;
  • Intel BX80569Q9550 | Data Sheet - Page 50
    Electrical Specifications Figure 2-13. V95CC0U0NSCeOrRieEsStatic and Transient Tolerance for the Intel® Itanium® Processor Normalized VccUnCore (V) 0.0150 -0.0050 -0.0250 -0.0450 -0.0650 -0.0850 -0.1050 -0.1250 -0.1450 -0.1650 0 VccUnCore Tolerance Band VccUnCore ACMax (V) VccUnCore DCMax (V)
  • Intel BX80569Q9550 | Data Sheet - Page 51
    Electrical Specifications Table 2-24. 9V5CC0C0OSReErSietsatic and Transient Tolerance for the Intel® Itanium® Processor Core Current (A) Voltage Deviation VSS pins. Refer to the Ararat II Voltage Regulator Module Design Guide for socket load line guidelines and VR implementation. 4. VDC(max)=VID
  • Intel BX80569Q9550 | Data Sheet - Page 52
    factor of 100%. Overshoot and Undershoot Specifications for the Intel® Itanium® Processor 9300 Series Table 2-25. Overshoot and Undershoot Specifications For Differential Intel® QuickPath Interconnect and Intel® SMI and Single-Ended Signals for the Intel® Itanium® Processor 9300 Series (Sheet 1 of
  • Intel BX80569Q9550 | Data Sheet - Page 53
    337 -0.525 -0.337 Max 1.54 1.7 1.54 Unit V V V V V V 2.6.5.2.2 Overshoot and Undershoot Specifications for the Intel® Itanium® Processor 9500 Series Table 2-26. Overshoot and Undershoot Specifications For Differential Intel® QuickPath Interconnect and Intel® SMI and Single-Ended Signals for the
  • Intel BX80569Q9550 | Data Sheet - Page 54
    3. Voltage Regulator Module Design See Intel® Itanium® 9300 Series GanudideInoter lt®heItaAnraiuramt pins at the bottom of the package. Table 2-29. TAP and System Management Group DC Specifications Symbol Parameter Min Max Unit Notes VIL VIH VOH VOL IOL IILeak IOLeak Input Low Voltage
  • Intel BX80569Q9550 | Data Sheet - Page 55
    with pin held at VSS. Unit V V µA Notes 1 1 1, 2 2.6.6.2 SVID Group DC Specifications for the Intel® Itanium® Processor 9500 Series The Intel® Itanium® Processor 9500 Series implements a Serial VID BUS that is used to transfer power management information between the microprocessor and the five
  • Intel BX80569Q9550 | Data Sheet - Page 56
    ensure Vpin of 1.1 V. Table 2-35. PIROM Signal Group DC Specifications Symbol Parameter Min TYP Max Unit VIL VIH VOL2 VOL1 IILeak IOLeak operating range T = -40 °C to +88 °C; Vcc = +1.7 V to +3.6 V. Notes 2,1 2,1 2 2 2 2 56 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 57
    voltage regulators. The VID_VCCCORE and VID_VCCUNCORE specifications for the Intel® Itanium® Processor 9300 Series and 9500 Guide for the Intel® Itanium® Processor 9300 Series processor or the Ararat II Voltage Regulator Module Design Guide for the Intel® Itanium® Processor 9500 Series. Intel
  • Intel BX80569Q9550 | Data Sheet - Page 58
    Electrical Specifications 2.7.1 Core and Uncore Voltage Identification for the Intel® Itanium® Processor 9300 Series Table 2-36. Intel® Itanium® Processor 9300 Series VCCCORE (VID_VCCCORE) and VCCUNCORE and (VID_VCCUNCORE) Voltage Identification Definition for Ararat (Sheet 1 of 2) Hex 00 01 02
  • Intel BX80569Q9550 | Data Sheet - Page 59
    Electrical Specifications Table 2-36. Intel® Itanium® Processor 9300 Series VCCCORE (VID_VCCCORE) and 1 1 OFF 2.7.2 Core and Uncore Voltage Identification for the Intel® Itanium® Processor 9500 Series Table 2-37. Intel® Itanium® Processor 9500 Series VCCCORE (VID_VCCCORE) and VCCUNCORE and
  • Intel BX80569Q9550 | Data Sheet - Page 60
    Electrical Specifications Table 2-37. Intel® Itanium® Processor 9500 Series 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 VID 7 VID6 VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 VID (V) 0 0 0 1 0 1 1 0 0.355 0 0 0 1 0 1 1 1 0.360 0 0 0 1 1 0 0 0 0.365 0 0
  • Intel BX80569Q9550 | Data Sheet - Page 61
    Electrical Specifications Table 2-37. Intel® Itanium® Processor 9500 Series 1 0 1 1 0 0 0 1.325 D9 1 1 0 1 1 0 0 1 1.330 DA 1 1 0 1 1 0 1 0 1.335 DB 1 1 0 1 1 0 1 1 1.340 DC 1 1 0 1 1 1 0 0 1.345 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 61
  • Intel BX80569Q9550 | Data Sheet - Page 62
    DE 1 1 0 1 1 1 1 0 1.355 DF 1 1 0 1 1 1 1 1 1.360 E0 1 1 1 0 0 0 0 0 1.365 E1 1 1 1 0 0 0 0 1 1.370 E2 cache voltage for the Intel® Itanium® Processor 9300 Series. The VID_VCCCACHE specification for the processor is supported by the Ararat I Regulator Module Design Guide
  • Intel BX80569Q9550 | Data Sheet - Page 63
    Specifications The processor uses the VID_VCCCACHE value to support level. See the Ararat I Regulator Module Design Guide for more details. Table 2-38. Cache (VID_VCCCACHE) Voltage Identification Definition for Ararat Hex 00 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 63
  • Intel BX80569Q9550 | Data Sheet - Page 64
    one cpu is from stepping N, and another cpu is from the next stepping, N+1, then Similarly CPUN is not compatible with CPUN+2. CPUN and CPUN+1 are compatible. 2. All CPUs in the system or hard partition must have the same core clock speed or speed range and the same cache size. 3. All Intel
  • Intel BX80569Q9550 | Data Sheet - Page 65
    Figure 2-17 and Figure 2-18, timing specifications for the elapsed time taken for an Guide for the Intel® Itanium® Processor 9300 Series and the Ararat II Voltage Regulator Module Design Guide for the Intel Intel® Itanium® Processor 9500 Series requires a minimum of 15 ms. For platforms that use
  • Intel BX80569Q9550 | Data Sheet - Page 66
    Specifications 2.11.1 Supported Power-up Voltage Sequence for the Intel® Itanium® Processor 9300 Series Figure 2-17. Supported Power-up Voltage Sequence Timing Requirements for the Intel® Itanium® Processor 9300 Series VCC33_SM (3.3v) PROCTYPE >1uS >0uS pulled to VSS on package for Intel Cache
  • Intel BX80569Q9550 | Data Sheet - Page 67
    Electrical Specifications 2.11.2 Supported Power-up Voltage Sequence for the Intel® Itanium® Processor 9500 Series Figure 2-18. Supported Power-up Sequence Timing Requirements for Intel® Itanium® Processor 9500 Series >0us VCCSTBY33 (3.3V) PROCTYPE Pulled to 3.3VSM pin on platform VCC (12V)
  • Intel BX80569Q9550 | Data Sheet - Page 68
    Electrical Specifications 2.11.3 Power-up Voltage Sequence Timing Intel® Itanium® Processor 9500 Series Min >0 0 >0 >0 >1 >1 1 0.05 0.05 0.05 >0 >0 10 15 Max 1000 200 200 5 8 3 2.5 3 Unit μs ms μs μs μs ms ms ms ms ms ms ms ms ms ms 2.12 Supported Power-down Voltage Sequence The supported
  • Intel BX80569Q9550 | Data Sheet - Page 69
    Electrical Specifications All signal inputs on VCCIO plane can power down with VCCIO Figure 2-19. Supported Power-down Voltage Sequence Timing Requirements RESET_N tR ESET_N A s interpreted as a NodeID bit during cold reset and Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 69
  • Intel BX80569Q9550 | Data Sheet - Page 70
    Electrical Specifications Figure 2-20. RESET_N and SKITID Timing for Warm and Cold Resets COLD T4 RESET_N deasserted pulse width T5 RESET_N asserted pulse width (Intel® Itanium® Processor 9300 Series) T5 RESET_N asserted pulse width (Intel® Itanium® Processor 9500 Series) T6 SKTID[2:0] (as
  • Intel BX80569Q9550 | Data Sheet - Page 71
    Electrical Specifications Table 2-40. RESET_N and SKTID Timing (Sheet 2 of 2) Parameter Description (TAP) Connection The recommended TAP connectivity is detailed in the Intel® Itanium® Platform Debug Port Design Guide (DPDG). § Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 71
  • Intel BX80569Q9550 | Data Sheet - Page 72
    Electrical Specifications 72 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 73
    . Table 3-2 is a listing of all processor package bottom side pins ordered by pin number. All pins are defined for both Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series except where noted. 3.1.1 Package Bottom Pin Listing by Pin Name Table 3-1. Pin List by Pin Name
  • Intel BX80569Q9550 | Data Sheet - Page 74
    I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential O Differential O Differential O Differential O 74 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 75
    I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 75
  • Intel BX80569Q9550 | Data Sheet - Page 76
    I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I 76 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 77
    I Differential I Differential O Differential O Differential O Differential O Differential O Differential O Differential O Differential O Differential O Differential O Differential O Differential O Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 77
  • Intel BX80569Q9550 | Data Sheet - Page 78
    I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I 78 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 79
    by Pin Name (Sheet 14 of 33) Pin Number AL6 AL7 V4 W1 V2 U1 T1 N3 M1 L3 L1 P1 J2 W4 W2 V3 V1 T2 N2 N1 M3 L2 P2 K2 AK8 AJ7 AH6 AF7 AF6 AC4 AB3 O Differential O Differential O Differential O Differential O Differential O Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 79
  • Intel BX80569Q9550 | Data Sheet - Page 80
    I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential I Differential O Differential O Differential O Differential O 80 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 81
    Type Direction Differential O Differential O Differential O Differential O I I I O O O O O I O I I I I Power/Other I Power/Other I Power/Other I Power/Other I/O O I O I I Power/Other I I Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 81
  • Intel BX80569Q9550 | Data Sheet - Page 82
    RSVD M13 RSVD M20 RSVD M21 RSVD M36 RSVD M4 RSVD P10 RSVD (Intel® Itanium® Processor 9300 Series) SVID_CLK2 (Intel® Itanium® Processor 9500 Series) P27 RSVD R10 RSVD (Intel® Itanium® Processor 9300 Series) SVID_DATIO (Intel® Itanium® Processor 9500 Series) R27 RSVD T11 RSVD
  • Intel BX80569Q9550 | Data Sheet - Page 83
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 83
  • Intel BX80569Q9550 | Data Sheet - Page 84
    /Other VCCIO_FBD Power/Other VCCIO_FBD Power/Other VFUSERM I VR_FAN_N O VR_THERMALERT_N O VR_THERMTRIP_N O VROUTPUT_ENABLE0 I VRPWRGD (Intel® O Itanium® Processor 9300 Series) VR_READY2 (Intel® Itanium® Processor 9500 Series) VSS Power/Other VSS Power/Other VSS Power/Other
  • Intel BX80569Q9550 | Data Sheet - Page 85
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 85
  • Intel BX80569Q9550 | Data Sheet - Page 86
    Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other 86 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 87
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 87
  • Intel BX80569Q9550 | Data Sheet - Page 88
    O AH8 XDPOCPD[0]_N I/O AG8 XDPOCPD[1]_N I/O AJ9 XDPOCPD[2]_N I/O AG9 XDPOCPD[3]_N I/O AH9 XDPOCPD[4]_N I/O AG10 XDPOCPD[5]_N I/O AJ10 XDPOCPD[6]_N I/O AK10 XDPOCPD[7]_N I/O 88 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 89
    I Power/Other Power/Other Power/Other Differential O Differential O Differential O Power/Other Differential O Differential O Power/Other Differential I Differential I Power/Other Differential O Power/Other Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 89
  • Intel BX80569Q9550 | Data Sheet - Page 90
    O Power/Other Differential I Differential I Power/Other Power/Other Differential I Differential I Power/Other Differential O Power/Other Differential O Power/Other Power/Other Power/Other Power/Other 90 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 91
    O Differential O Power/Other Differential O Differential O Power/Other Differential I Power/Other Differential I Differential I Differential I Differential I Differential I Power/Other Differential O Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 91
  • Intel BX80569Q9550 | Data Sheet - Page 92
    Differential O Power/Other Differential I Differential I Power/Other Power/Other Differential I Differential I Differential I Differential I Power/Other Differential O Differential O Differential O I/O 92 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 93
    Power/Other AL36 CSI1RPDAT[9] Differential I AL37 CSI1RNDAT[9] Differential I AL38 VROUTPUT_ENABLE0 I AM1 VRPWRGD (Intel® O Itanium® Processor 9300 Series) VR_READY (Intel® Itanium® Processor 9500 Series) AM2 VSS Power/Other AM3 FBD0NBIAP[9] Differential I AM4 VCCIO_FBD
  • Intel BX80569Q9550 | Data Sheet - Page 94
    I I Differential I Power/Other Differential I Power/Other Differential I Differential I Power/Other Differential I Power/Other I/O Power/Other Power/Other Differential I Differential I Differential I 94 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 95
    I Power/Other Differential I Power/Other Differential I Differential I Power/Other Differential I Power/Other Differential I Differential I Differential I Differential I Power/Other Differential I Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 95
  • Intel BX80569Q9550 | Data Sheet - Page 96
    I Power/Other Differential I Differential I Power/Other Differential I Power/Other Differential I Differential I Power/Other Differential I Power/Other Power/Other Power/Other Differential I Differential I 96 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 97
    /Other Power/Other Differential I Differential I Differential I Differential I Power/Other Differential I Differential I Differential I Power/Other Power/Other Differential I Differential I Differential I Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 97
  • Intel BX80569Q9550 | Data Sheet - Page 98
    I Differential I Power/Other Differential I Differential I Differential O Differential O Power/Other Power/Other Power/Other Differential O Differential O Power/Other Differential O Differential O 98 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 99
    /Other Differential O Differential O Differential O Differential O Power/Other Differential O Power/Other Differential O Differential O Power/Other Differential O Power/Other Differential I Differential I Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 99
  • Intel BX80569Q9550 | Data Sheet - Page 100
    O Differential O Power/Other Differential O Differential O Differential O Differential O Power/Other Power/Other Differential I Differential I Differential I Power/Other Power/Other Differential O 100 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 101
    K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37 K38 L1 L2 L3 L4 Pin Name VSS FBD1NBIDN[9] FBD1NBIDP[9] VSS FBD1NBIDP[11] FBD1NBICP[6] FBD1NBICN[6] O Power/Other Differential O Differential I Differential I Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 101
  • Intel BX80569Q9550 | Data Sheet - Page 102
    CSI0RNDAT[12] CSI0RPDAT[12] FBD0SBOAN[9] FBD0SBOAP[9] VSS VSS FBD1NBIDN[12] FBD1NBIDP[12] FBD1NBICLKDP0 VSS FBD1NBICN[5] RSVD1 (Intel® Itanium® Processor 9300 Series) SVID_CLK22 (Intel® Itanium® Processor 9500 Series) TCK TDI RSVD VSS FLASHROM_CS[1]_N CSI2TNDAT[12] CSI2TPDAT[12] CSI2TNDAT[15] VSS
  • Intel BX80569Q9550 | Data Sheet - Page 103
    3-2. Pin List by Pin Number (Sheet 30 of 32) Pin Number Pin Name Signal Buffer Type Direction T11 RSVD1 (Intel® Itanium® Processor 9300 Series) SVID_ALERT_N2 (Intel® Itanium® Processor 9500 Series) T12 VFUSERM I T27 VCCIO Power/Other T28 FLASHROM_DATI I T29 VSS Power/Other T30
  • Intel BX80569Q9550 | Data Sheet - Page 104
    Differential I Differential I Power/Other Differential I Power/Other I Power/Other Power/Other Power/Other Differential O Power/Other Differential O Differential O Power/Other Differential I Differential I 104 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 105
    Top-Side J1 Connector Two-Dimensional Table 3.2.1.1 Top-Side J1 Connector Two-Dimensional Table for the Intel® Itanium® Processor 9300 Series Table 3-3 is a two dimensional table of the Intel® Itanium® Processor 9300 Series package top-side J1 connector. Table 3-3. Top-Side J1 Connector Two
  • Intel BX80569Q9550 | Data Sheet - Page 106
    AU AV NO CONNECT AW AY 1 2 3 4 3.2.1.2 Top-Side J1 Connector Two-Dimensional Table for the Intel® Itanium® Processor 9500 Series Table 3-4 is a two-dimensional table of the Intel® Itanium® Processor 9500 Series package top-side J1 connector. Table 3-4. Top-Side J1 Connector Two-Dimensional
  • Intel BX80569Q9550 | Data Sheet - Page 107
    Pin Listing Table 3-4. Top-Side J1 Connector Two-Dimensional Table (Intel® Itanium® Processor 9500 Series) (Sheet 2 of 3) 1 F G H J K L M N P R T U V W Y AA T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT 1 2 3 4 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 107
  • Intel BX80569Q9550 | Data Sheet - Page 108
    -Side J2 Connector Two-Dimensional Table 3.2.2.1 Top-Side J2 Connector Two-Dimensional Table for the Intel® Itanium® Processor 9300 Series Table 3-5 is a two-dimensional table of the Intel® Itanium® Processor 9300 Series Processor package top-side J2 connector. Table 3-5. Top-Side J2 Connector
  • Intel BX80569Q9550 | Data Sheet - Page 109
    Pin Listing Table 3-5. Top-Side J2 Connector Two-Dimensional Table (Intel® Itanium® Processor 9300 Series) (Sheet 2 of 2) 1 W the Intel® Itanium® Processor 9500 Series Table 3-6 is a two-dimensional table of the Intel® Itanium® Processor 9500 Series package top-side J2 connector. Intel® Itanium
  • Intel BX80569Q9550 | Data Sheet - Page 110
    Pin Listing Table 3-6. Top-Side J2 Connector Two-Dimensional Table (Intel® Itanium® Processor 9500 Series) (Sheet 1 of 2) 1 A NO CONNECT B NO CONNECT C RESERVED D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK 2 3 NO CONNECT NO CONNECT
  • Intel BX80569Q9550 | Data Sheet - Page 111
    Top-Side J3 Connector Two-Dimensional Table 3.2.3.1 Top-Side J3 Connector Two-Dimensional Table for the Intel® Itanium® Processor 9300 Series Table 3-7 is a two-dimensional table of the Intel® Itanium® Processor 9300 Series package top-side J3 connector. Table 3-7. Top-Side J3 Connector Two
  • Intel BX80569Q9550 | Data Sheet - Page 112
    Pin Listing Table 3-7. Top-Side J3 Connector Two-Dimensional Table (Intel® Itanium® Processor 9300 Series) (Sheet 2 of 2) 1 N P R T U V W Y AA AB AC AF AG AH AJ AK AL AM AN AP AR AT AU AV NO CONNECT AW AY 1 2 3 4 112 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 113
    ® Processor 9500 Series package top-side J3 connector. Table 3-8. Top-Side J3 Connector Two-Dimensional Table (Intel® Itanium® Processor 9500 Series) (Sheet 1 of 2) 1 2 3 4 A NO CONNECT NO CONNECT A B VR_FAN_N C NO CONNECT D E F G H J K L M N P R T U V W Y AA AB AC
  • Intel BX80569Q9550 | Data Sheet - Page 114
    Top-Side J4 Connector Two-Dimensional Table 3.2.4.1 Top-Side J4 Connector Two-Dimensional Table for the Intel® Itanium® Processor 9300 Series Table 3-9 is a two-dimensional table of the Intel® Itanium® Processor 9300 Series package top-side J4 connector. Table 3-9. Top-Side J4 Connector Two
  • Intel BX80569Q9550 | Data Sheet - Page 115
    Pin Listing Table 3-9. Top-Side J4 Connector Two-Dimensional Table (Intel® Itanium® Processor 9300 Series) (Sheet 2 of 2) 1 K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU VCCIO AV
  • Intel BX80569Q9550 | Data Sheet - Page 116
    ® Itanium® Processor 9500 Series package top-side J4 connector. Table 3-10. Top-Side J4 Connector Two-Dimensional Table (Intel® Itanium® Processor 9500 Series) (Sheet 1 of 2) 1 A NO CONNECT B RESERVED C RESERVED D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG
  • Intel BX80569Q9550 | Data Sheet - Page 117
    Pin Listing Table 3-10. Top-Side J4 Connector Two-Dimensional Table (Intel® Itanium® Processor 9500 Series) (Sheet 2 of 2) 1 AH AJ AK AL AM AN AP AR AT AU AH AJ AK AL AM AN AP AR AT AU AV NO CONNECT AW AY 1 2 3 4 § Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 117
  • Intel BX80569Q9550 | Data Sheet - Page 118
    Pin Listing 118 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 119
    Specifications The Intel® Itanium® Processor 9300 Series and 9500 Series are packaged in a FC-LGA package that interfaces with the motherboard via an LGA1248 socket. The package top side consists of lands that interface with a LGA connector for direct power delivery to the core, cache and
  • Intel BX80569Q9550 | Data Sheet - Page 120
    4.1 Mechanical Specifications Package Mechanical Drawing The package mechanical drawings are shown in Figure 4-2, Figure 4-3, Figure 4-4 and Figure 4-5. The package mechanical drawings for the Intel® Itanium® Processor 9500 Series processor are shown in Figure 4-6, Figure 4-7, Figure 4-8 and Figure
  • Intel BX80569Q9550 | Data Sheet - Page 121
    Mechanical Specifications 4.2 Intel® Itanium® Processor 9300 Series Figure 4-2. Intel® Itanium® Processor 9300 Series Package Drawing (Sheet 1 of 4) Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 121
  • Intel BX80569Q9550 | Data Sheet - Page 122
    Mechanical Specifications Figure 4-3. Intel® Itanium® Processor 9300 Series Processor Package Drawing (Sheet 2 of 4) 122 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 123
    Mechanical Specifications Figure 4-4. Intel® Itanium® Processor 9300 Series Package Drawing (Sheet 3 of 4) Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 123
  • Intel BX80569Q9550 | Data Sheet - Page 124
    Mechanical Specifications Figure 4-5. Intel® Itanium® Processor 9300 Series Package Drawing (Sheet 4 of 4) 124 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 125
    Mechanical Specifications Figure 4-6. Intel® Itanium® Processor 9500 Series Package Drawing (Sheet 1 of 4) Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 125
  • Intel BX80569Q9550 | Data Sheet - Page 126
    Mechanical Specifications Figure 4-7. Intel® Itanium® Processor 9500 Series Package Drawing (Sheet 2 of 4) 126 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 127
    Mechanical Specifications Figure 4-8. Intel® Itanium® Processor 9500 Series Package Drawing (Sheet 3 of 4) Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet 127
  • Intel BX80569Q9550 | Data Sheet - Page 128
    Mechanical Specifications Figure 4-9. Intel® Itanium® Processor 9500 Series Package Drawing (Sheet 4 of 4) 128 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 129
    Intel® Itanium® 9500 Series Processor keepout zones. 4.4 Package Loading Specifications Table 4-1 provides dynamic and static load specifications use condition. Also, any mechanical system or component testing should not exceed the maximum limits. The processor package substrate should not be used
  • Intel BX80569Q9550 | Data Sheet - Page 130
    FCLGA Durability Limit 15 4.6 Processor Mass Specifications The typical mass of the Intel® Itanium® Processor 9300 Series and 9500 Identification): Is a unique number which can be used for the purpose of tracking the processor. It is used by Intel to retrieve processor related information. 2. FPO
  • Intel BX80569Q9550 | Data Sheet - Page 131
    Mechanical Specifications Figure 4-10. Processor Marking Zones A Top Side H G F Bottom Side § Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet C B E 131
  • Intel BX80569Q9550 | Data Sheet - Page 132
    Mechanical Specifications 132 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 133
    benchmark suites. Boost frequency is available when the processor is not power limited. The Intel® Itanium® Processor 9500 Series enables Intel® Turbo Boost Technology featuring keep the processor at TDP for high activity applications. Instruction dispersal is lowered in a core to keep the activity
  • Intel BX80569Q9550 | Data Sheet - Page 134
    TCONTROL THERMALERT M ax O perating Te m perature D iag ram not to scale Tim e 5.1.1 Digital Thermometer The Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series uses a thermal sensing device called Digital Thermometer (DT) to read the values from the thermal sensors
  • Intel BX80569Q9550 | Data Sheet - Page 135
    the die temperature using thermal sensors placed steps (a) to (d). a. If T>=TPROCHOT and the Intel® Itanium® Processor 9300 Series is operating at boost frequency, then the thermal management system will instruct supported P-state. Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 136
    Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series thermal management features , limiting the processor to executing only one instruction per cycle. When the PROCHOT threshold is be found in the Intel® Itanium® Processor Family Interrupt Architecture Guide. There is a
  • Intel BX80569Q9550 | Data Sheet - Page 137
    Intel® Itanium® Processor 9300 Series. For the Intel® Itanium® Processor 9500 Series, the default values are 0°C. This signal can be used by the platform to implement thermal regulation features design. See Intel® Itanium® Processor 9300 Series Thermal Mechanical Design Guide for additional guidance
  • Intel BX80569Q9550 | Data Sheet - Page 138
    and also transition to the voltage and frequency of the lowest supported P-state. Time limits and CMCI generation are the same as Intel® Itanium® Processor 9500 Series package allows the Ararat Voltage Regulator to signal to the platform when it approaches its own thermal limits. The specific
  • Intel BX80569Q9550 | Data Sheet - Page 139
    is limited to 250 W for the 185 W SKUs. Thermal Specification for the Intel® Itanium® Processor 9500 Series Processor TDP - Thermal Design Power . That is when DT readout is equal to zero. TCASE cannot be used as proxy for power dissipation due to the variation in work load imbalances between
  • Intel BX80569Q9550 | Data Sheet - Page 140
    (FRU: Field Replaceable Unit), or installation onto a board given the multitude of attach methods, and board types used by customers. Provided as general guidance only, Intel® board products are specified and certified to meet the following temperature and humidity limits (Non-Operating Temperature
  • Intel BX80569Q9550 | Data Sheet - Page 141
    bias. Storage within these limits will not affect the long-term reliability of the device. For functional operation, please refer to the processor case temperature specifications. 2. These ratings apply to the Intel component and do not include the tray or packaging. 3. Failure to adhere to this
  • Intel BX80569Q9550 | Data Sheet - Page 142
    Thermal Specifications 142 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 143
    6.4. The processor SMBus implementation uses the clock and data signals of the System Management Bus (SMBus) Specification. Layout and routing guidelines are available in the Intel® Itanium® 9300 Series and Intel® Itanium® 9500 Series Platform Design Guide. Intel® Itanium® Processor 9300 Series
  • Intel BX80569Q9550 | Data Sheet - Page 144
    section of PIROM containing Processor Features Data 0x72; 0x00 if not present 11 0Bh Other Data Address Hex Byte pointer Pointer to the section of PIROM 0x7D; 0x00 if not containing Processor "Other" Data present 12 0Ch RESERVED Hex Reserved for future use 0Ch = 0x00 13 0Dh 0Dh
  • Intel BX80569Q9550 | Data Sheet - Page 145
    in four 4-bit Hex digits (in mV) Core Voltage Tolerance, High Core Voltage Tolerance, Low RESERVED Checksum Maximum Intel® QuickPath Interconnect Link Transfer Rate 2 Hex digits Edge finger tolerance in mV, + 2 Hex digits Edge finger tolerance in mV, - Hex Reserved for future use Hex Add
  • Intel BX80569Q9550 | Data Sheet - Page 146
    4 bcd digits Size of the Cache, in MB. 4 bcd digits (Intel® Itanium® Processor 9300 Series) 2 Hex digits (Intel® Itanium® Processor 9500 Series) Voltage in four 4-bit bcd digits (in mV) (Intel® Itanium® Processor 9300 Series) Reserved for future use (Intel® Itanium® Processor 9500 Series) 24MB
  • Intel BX80569Q9550 | Data Sheet - Page 147
    number: 00b MSB 2 Bits (MSB) 6 Bits reserved (LSB) (Intel® Itanium® Processor 9300 000000b Reserved (Intel® Itanium® Processor 9300 Series) Series) RESERVED (Intel® Itanium® Processor 9500 Series) 85 55h Checksum Reserved for future use for Intel® 0x00 (Intel® Itanium® Itanium® Processor
  • Intel BX80569Q9550 | Data Sheet - Page 148
    RESERVED Checksum Data Type 16 Digit Hex Number Description 64 - bit identification number; may have padded zeros. Example 4 bcd digits 4 bcd digits Hex Hex Base Core Frequency for this part Reserved for future use (Intel® Itanium® processor 9300 series) Nominal operating uncore frequency in
  • Intel BX80569Q9550 | Data Sheet - Page 149
    Data Type Description 114 72h Processor Core Feature 115 73h Flags 116 74h 117 75h Features 8 digit Hex number From CPUID Example Flag EEPROM Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series support a Scratch EEPROM section, which may be used for other
  • Intel BX80569Q9550 | Data Sheet - Page 150
    Management Bus Interface 6.2.3 PIROM and Scratch EEPROM Supported SMBus Transactions The PIROM responds to two SMBus 7-bits 1 1 8-bits 1 8-bits 1 1 6.3 Memory Component Addressing The Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series PIR_A[1:0] pins are used
  • Intel BX80569Q9550 | Data Sheet - Page 151
    SCL WP A2 A1 A0 VCC SMBDAT SMBCLK SPDDAT SPDCLK VSS 0.1uF C579 PIR_SDA PIR_SCL SM_WP PIR_A1 PIR_A0 VCC33_SM To/From Platform Intel® Itanium® processor Die U1 To/From Platform BOOTMODE[1] BOOTMODE[0] THERMALERT_N SKTID[0] SKTID[1] SKTID[2] BO OTMO DE[1] BOOTMODE[0] THERMALERT_N SKTID[0] SKTID
  • Intel BX80569Q9550 | Data Sheet - Page 152
    specs. The sample or production field is a two-bit, Intel® Itanium® Processor 9500 Series is 0x01. Processor Core Data This section contains silicon-related data relevant to the processor cores. CPUID Offset 22h-25h contains a copy of the results in EAX[31:0] from Function 1 of the CPUID instruction
  • Intel BX80569Q9550 | Data Sheet - Page 153
    voltage tolerances, high and low respectively. These use a decimal to Hexadecimal conversion. Example: 19 support only (for Intel® Itanium® Processor 9300 Series), 02h is Intel® 7500 Scalable Memory Buffer support only, and 04h represents support for Intel® 7510/7520 Scalable Memory Buffers (Intel
  • Intel BX80569Q9550 | Data Sheet - Page 154
    if processors and Intel® 75xx Scalable Memory Buffers support the same Intel® SMI transfer rate. Six 4-bit BCD digits are used to provide the Intel® Itanium® Processor 9500 Series. Cache Voltage Tolerance Offset 4Ah and 4Bh contain the cache voltage tolerances, high and low respectively. These use
  • Intel BX80569Q9550 | Data Sheet - Page 155
    at offset 4Fh-53h used to capture package technology. Electronic Signature Offset 5Dh-64h contains a unique 64-bit identification number. Base Frequency (Core) Offset 65h Uncore) Offset 67h-68h contain the uncore frequency for the Intel® Itanium® Processor 9500 Series. Example: a processor with
  • Intel BX80569Q9550 | Data Sheet - Page 156
    powering on the processor. 6.4.9.1 Processor Core Feature Flags For the Intel® Itanium® Processor 9300 Series, offset 72h-75h contains a copy of results in EDX[31:0] from Function 1 of the CPUID instruction. These details provide instruction and feature support by product family. These fields are
  • Intel BX80569Q9550 | Data Sheet - Page 157
    Core Data Processor Uncore Data Cache Data Package Data Part Number Data Thermal Reference Data Feature Data Other Data Checksum Address 0101100 First step: add the bytes. AA + 44 + 5C = 01001010 Second step: take 2's complement. 10110101 +1 = 10110110 Checksum is 0xB6. § Intel® Itanium
  • Intel BX80569Q9550 | Data Sheet - Page 158
    System Management Bus Interface 158 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 159
    Intel® Itanium® Processor 9500 Series External Design Specification. To pull any of these inputs high, they should be strapped to VCCIO through a pull-up resistor, and to pull these low, they should be strapped to GND. These pins are sampled during all resets except warm-logic reset. CPU bit
  • Intel BX80569Q9550 | Data Sheet - Page 160
    port 5 Data, lane 0, transmit signal and positive bit of the differential pair. O Side band signaling for system management. Refer to the Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series Platform Design Guide for pin considerations. O Side band signaling for
  • Intel BX80569Q9550 | Data Sheet - Page 161
    0 signal of channel A and positive bit of the differential pair. I These signals are spare lanes, and are intended for Reliability, Availability, and Serviceability (RAS) coverage on the Intel® Itanium® 9500 Processor Series. These signals are not used by Intel® Itanium® 9300 Processor Series
  • Intel BX80569Q9550 | Data Sheet - Page 162
    0 signal of channel C and positive bit of the differential pair. I These signals are spare lanes, and are intended for Reliability, Availability, and Serviceability (RAS) coverage on the Intel® Itanium® 9500 Processor Series. These signals are not used by Intel® Itanium® 9300 Processor Series
  • Intel BX80569Q9550 | Data Sheet - Page 163
    Intel® Itanium® Processor 9500 Series Platform Design Guide for a detailed signal description. The header mode is selected by the LRGSCLSYS strapping pin value sampled only during COLD reset. LRGSCLSYS, when tied to VCCIO using features of the Intel® Itanium® Processor 9300 Series and Intel®
  • Intel BX80569Q9550 | Data Sheet - Page 164
    External Design Specification for limitations. This a source-synchronous clock used by the processor to transmit voltage ID data to the Ararat II voltage regulator. This is an open drain signal. See Ararat II Voltage Regulator Module Design Guide for termination requirements for the Intel® Itanium
  • Intel BX80569Q9550 | Data Sheet - Page 165
    (Voltage ID) pads are used to support automatic selection of VCCCORE, VCCUNCORE and VCCCACHE by the Intel® Itanium® 9300 Processor Series. fan speed (airflow). See Ararat 170W Voltage Regulator Module Design Guide and /or Ararat II Voltage Regulator Module Design Guidefor platform-specific
  • Intel BX80569Q9550 | Data Sheet - Page 166
    Intel® Itanium® 9300 Processor Series only). See Ararat 170W Voltage Regulator Module Design Guide and/or Ararat II Voltage Regulator Module Design Guide to VCCCORE, VCCUNCORE, and VCCCACHE are stable within their voltage specification, and indicates that the Ararat VR start up sequence is completed
  • Intel BX80569Q9550 | Data Sheet - Page 167
    Voltage Identification for the Intel® Itanium® Processor 9500 Series 59 2.8 Cache Voltage Identification (Intel® Itanium® Processor 9300 Series only 62 2.9 RSVD, Unused, and DEBUG Pins 63 2.10 Mixing Processors 64 2.11 Supported Power-up Voltage Sequence 64 2.11.1 Supported Power-up Voltage
  • Intel BX80569Q9550 | Data Sheet - Page 168
    Data 152 6.4.4 Processor Uncore Data 153 6.4.5 Cache Data 154 6.4.6 Package Data 155 6.4.7 Part Number Data 155 6.4.8 Thermal Reference Data 155 6.4.9 Feature Data 156 6.4.10 Other Data 157 6.4.11 Checksums 157 7 Signal Definitions 159 168 Intel® Itanium® Processor 9300 Series and 9500
  • Intel BX80569Q9550 | Data Sheet - Page 169
    51 VR Sense Point (Representation 57 Supported Power-up Voltage Sequence Timing Requirements for the Intel® Itanium® Processor 9300 Series 66 Supported Power-up Sequence Timing Requirements for Intel® Itanium® Processor 9500 Series 67 Supported Power-down Voltage Sequence Timing Requirements
  • Intel BX80569Q9550 | Data Sheet - Page 170
    170 Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet
  • Intel BX80569Q9550 | Data Sheet - Page 171
    30 2-31 2-32 2-33 Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series Feature Comparison 19 Signals with RTT 24 Signal Groups 24 Intel® QuickPath Interconnect/Intel® Scalable Memory 'Interconnect Reference Clock Specifications 26 Intel® Itanium® Processor 9300 Series
  • Intel BX80569Q9550 | Data Sheet - Page 172
    9300 Series 134 Thermal Sensor Accuracy Distribution for the Intel® Itanium® Processor 9500 Series 135 Thermal Specification for the Intel® Itanium® Processor 9300 Series 139 Thermal Specification for the Intel® Itanium® Processor 9500 Series Processor ....... 139 Storage Condition Ratings
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Reference Number: 322821-002
Intel
®
Itanium
®
Processor 9300
Series and 9500 Series
Intel
®
Itanium
®
Processor Quad-Core 1.86-1.73 GHz with 24 MB L3 Cache 9350
Intel
®
Itanium
®
Processor Quad-Core 1.73-1.60 GHz with 20 MB L3 Cache 9340
Intel
®
Itanium
®
Processor Quad-Core 1.60-1.46 GHz with 20 MB L3 Cache 9330
Intel
®
Itanium
®
Processor Quad-Core 1.46-1.33 GHz with 16 MB L3 Cache 9320
Intel
®
Itanium
®
Processor Dual-Core 1.60 GHz Fixed Frequency with 10 MB L3 Cache 9310
Intel
®
Itanium
®
Processor Eight-Core 2.53 GHz with 32 MB LLC Cache 9560
Intel
®
Itanium
®
Processor Four-Core 2.40 GHz with 32 MB LLC Cache 9550
Intel
®
Itanium
®
Processor Eight-Core 2.13 GHz with 24 MB LLC Cache 9540
Intel
®
Itanium
®
Processor Four-Core 1.73 GHz with 20 MB LLC Cache 9520
Datasheet
November 2012