Intel BX80569Q9550 Specification Update

Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Manual

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  • Intel BX80569Q9550 | Specification Update - Page 1
    Intel® Itanium® Processor 9300 Series and 9500 Series Specification Update November 2012 Reference Number: 323169-010
  • Intel BX80569Q9550 | Specification Update - Page 2
    Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel for use by Intel to identify products, technologies, or services in
  • Intel BX80569Q9550 | Specification Update - Page 3
    Contents Revision History ...4 Preface ...5 Identification Information 7 Summary Table of Changes 8 Intel® Itanium® Processor 9300 Series Errata 13 Intel® Itanium® Processor 9500 Series Errata 30 Intel® Itanium® Processor 9300 Series and 9500 Series Specification Update 3 November 2012
  • Intel BX80569Q9550 | Specification Update - Page 4
    replaced with S-SPEC numbers. Added two Stepping Summary Table. Added Intel® Itanium® Processor 9300 Series Errata 54,56,57,58,59,113,114. Added Intel® Itanium® Processor 9300 Series PAL Version 4.39. Removed Intel® Itanium® Processor 9300 Series Errata 18, 19, 30, 31 as this is not a supported
  • Intel BX80569Q9550 | Specification Update - Page 5
    ® Itanium® Processor 9500 Series Reference Manual - Software Development and Optimization Guide Intel® Itanium® Architecture Software Developer's Manual, Volumes 1 through 4 Intel® Itanium® Architecture Software Developer's Manual Specification Update Intel® Itanium® Processor 9500 Series Processor
  • Intel BX80569Q9550 | Specification Update - Page 6
    errors. These may cause the processor's behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. Documentation Changes and Clarifications are modifications
  • Intel BX80569Q9550 | Specification Update - Page 7
    Information Table 3. Intel® Itanium® Processor 9300 Series Stepping Summary S-Spec Number LBMX LBMW LBMU LBN2 LBMV LC3A LC39 LC38 LC3B LC37 Processor Number 9350 9340 9330 9320 9310 9350 9340 9330 9320 9310 Processor Stepping Revision E0 E0 E0 E0 E0 E0 E0 E0 E0 E0 CPUID 0020020404 0020020404
  • Intel BX80569Q9550 | Specification Update - Page 8
    to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations: Codes Used in Summary Tables Stepping X: (Blank box): Errata
  • Intel BX80569Q9550 | Specification Update - Page 9
    Table 5. Intel® Itanium® Processor 9300 Series Errata Summary (Sheet 1 of 3) Processor Stepping PAL Version E0 4.15 4.25 4.28 4.29 4. Error Lower 2 Bits Of IHA Have Read/Write Intel® SMI and Intel® QPI Intel® Itanium® Processor 9300 Series and 9500 Series Specification Update 9 November 2012
  • Intel BX80569Q9550 | Specification Update - Page 10
    Table 5. Intel® Itanium® Processor 9300 Series Errata Summary (Sheet 2 of 3) Processor Stepping PAL Version E0 4.15 4.25 4.28 4.29 4.30 4.37 4.39 Status 27 Hot Deassertion Hysteresis PAL_VP_CREATE does not perform reserved bit checking on the virtualization acceleration control (VAC) and
  • Intel BX80569Q9550 | Specification Update - Page 11
    Intel® Itanium® Processor 9300 Series Errata Summary (Sheet 3 of 3) Processor Stepping PAL Version E0 in S-spec parts Window PAL Returns No Information On Bus Log Overflow A Memory Update Operation May Not Complete Properly When An L2 Cache Line Encounters a Second Single Bit Data Error Intel Cache
  • Intel BX80569Q9550 | Specification Update - Page 12
    Table 6. Intel® Itanium® Processor 9500 Series Errata Summary Processor Stepping D0 8 X With 16-bit CRC Scalable Intel® QPI FPU Denormal SWA Priority Change PAL_PERF_MON_INFO Has Implementation Specific Requirements For cycles And retired Intel® QPI State PHY_RESET / PHY_REINIT Not Supported
  • Intel BX80569Q9550 | Specification Update - Page 13
    can poll Px[n]_PBOXMSCCTL.NO_RESPONSE_FROM_LL. If firmware finds this bit is asserted it can trigger a reset in the phy layer. Status: No Fix. 4. Bbox Violates Message Class Dependency Problem: The Intel® QuickPath Interconnect Specification does not allow an NCB to DRS dependency. The
  • Intel BX80569Q9550 | Specification Update - Page 14
    in the link. This can also occur on a reset where 16-bit CRC is changed to 8-bit CRC, or 8-bit CRC is changed to 16-bit CRC. This can possibly triggering ERROR# 301, "Rbox Intel® QuickPath Interconnect CRC Error" if enabled. Use the following flow when performing a link layer reset where the CRC
  • Intel BX80569Q9550 | Specification Update - Page 15
    .CRCEC following the PHY reset. Intel® QPI CRC Errors can occur if 16-bit rolling CRC is enabled and a link layer or PHY layer reset occurs. Status: No Fix. 9. Problem: Reset While In Calibration State Can Cause Hang On Intel® Scalable Memory Interconnect (Intel® SMI) A reset while in the
  • Intel BX80569Q9550 | Specification Update - Page 16
    accessed. This is not supported on the processor. Workaround: Ensure good parity is used in the route table. Status: No Fix. 15. Problem: Lower 2 Bits Of IHA Have Read/Write Behavior Volume 2 of the 2.2 Intel® Itanium® Architecture Software Developer's Manual, Section 3.3.5.9 "Interruption Hash
  • Intel BX80569Q9550 | Specification Update - Page 17
    20. Problem: Physical Damage To Intel® SMI Lane Can Cause Training To Fail Noise on an Intel® SMI lane Intel® SMI link to loop on fast resets. This does not affect Intel® QPI links. Implication: Error #617 is incorrectly logged. Intel® Itanium® Processor 9300 Series and 9500 Series Specification
  • Intel BX80569Q9550 | Specification Update - Page 18
    well as on all physical layer resets). If scrambling is disabled, this 2 cycle window only occurs on a physical layer reset. Status: No Fix. 23. Problem: Transmitter Parameter Values The Intel® Itanium® Processor 9300 Series and 9500 Series Datasheet defines the Transmitter Parameter Values for
  • Intel BX80569Q9550 | Specification Update - Page 19
    1.0, Electrical specifications. Workaround: None at this time. Status: No Fix. 24. Problem: L2i Fills In 1 Way Of Set When All Other Ways Are Valid And A Way Is Disabled In Set When Intel Cache Safe Technology disables any of the 8 ways in a set, the ways which are not disabled are used for the
  • Intel BX80569Q9550 | Specification Update - Page 20
    mV documented in the Intel® QuickPath Interconnect, Version 1.0, Electrical specifications for the parameter in the table below. Instead it uses a Min value of Workaround: None at this time. Status: No Fix. 28. Problem: Implication: Corrupted ALERT Frame Not Detected By Zbox Any corrupted ALERT
  • Intel BX80569Q9550 | Specification Update - Page 21
    complete the write without reissuing. The memory controller uses two Intel® SMI channels in lockstep for each cache line access, thus on a future read if one Fix. 32. Problem: PAL_SHUTDOWN Has Incorrect Index Volume 2 of the 2.2 Intel® Itanium® Architecture Software Developer's Manual, Table 11-39
  • Intel BX80569Q9550 | Specification Update - Page 22
    Problem: If the Rbox is blocked and unable to make forward progress for some period of time, and at the same time the Intel® QPI credits are used up (both VNA credits on an Intel® QPI link and VN0 DRS credits on the caching accessing the local Ubox in a specific traffic corner case. An ORB timeout
  • Intel BX80569Q9550 | Specification Update - Page 23
    . Problem: In A Virtualized Environment Guest OS IIB0/IIB1 Reads/Writes May Not Behave As Expected If Virtualization Acceleration is Enabled The Intel® Itanium® Architecture Software Developer's Manual Specification Update October 2009, Specification Change 16 adds "Interruption Instruction Bundle
  • Intel BX80569Q9550 | Specification Update - Page 24
    : Fixed in PAL 4.29. 42. Nested MCA may occur during recoverable MCA testing Problem: Recoverable MCA testing may result in a PAL hang. Implication: When testing recoverable MCAs Fixed in PAL 4.29. 24 November 2012 Intel® Itanium® Processor 9300 Series and 9500 Series Specifiication Update
  • Intel BX80569Q9550 | Specification Update - Page 25
    pended QR CMCI may not be cleared during the OS boot sequence Problem: A pended QR (charge rationing) CMCI prior to booting to the set there is a very small window which can cause an unexpected uncorrectable described in the QPI specification is not preserved on Intel® Itanium® Processor 9300
  • Intel BX80569Q9550 | Specification Update - Page 26
    : None at this time. Status: Fixed in PAL 4.30. 53. Problem: Intel® QPI State Machine Does Not Increment On Every Initialization Failure Instance When there is a link layer initialization failure, per the Intel® QPI specification the Intel® QPI logic should track such a failure in order to issue
  • Intel BX80569Q9550 | Specification Update - Page 27
    . These CSR fields cannot be used as expected for counting Intel® QPI link events. These fields should be treated as Reserved. Workaround: None identified. Status: No Fix. 56. Burst Of L3 Cache and L2 Cache Correctable Errors Observed On Some Processors Problem: A burst of correctable errors
  • Intel BX80569Q9550 | Specification Update - Page 28
    Occur In A Small Window Problem: If 3 errors (at when called for the Structure Specific Error Information (SSEI), PAL Cache Line Encounters a Second Single Bit Data Error Problem: If an L2 cache line has encountered a second single bit error and is in the process of being disabled by Intel Cache
  • Intel BX80569Q9550 | Specification Update - Page 29
    psp.hd Bit Set Problem: If an Intel Cache Safe Technology event Manual, but implication depends on the OS action/response to the "hardware damaged" set at SAL_CHECK. Workaround: None at this time. Status: Fixed in PAL 4.39. Intel® Itanium® Processor 9300 Series and 9500 Series Specification
  • Intel BX80569Q9550 | Specification Update - Page 30
    the Intel® Itanium® Processor 9500 Series will be referred to as "the processor". Mixing steppings of the processor in the same system is not supported. The processors in same system must have the same CPUID, Stepping, TDP, Core Frequency, and LLC cache size. 8. Problem: CRC Errors With 16 Bit
  • Intel BX80569Q9550 | Specification Update - Page 31
    if unsupported NodeIDs are accessed. This is not supported on the processor. Workaround: Ensure good parity is used in the route table. Status: No Fix. 20. Problem: Physical Damage To Intel® SMI Lane Can Cause Training To Fail Noise on an Intel® SMI lane can appear as a TS0 training header
  • Intel BX80569Q9550 | Specification Update - Page 32
    . Status: No Fix. 21. Northbound Intel® SMI CRC Persistent Error Can Cause South Bound CRCs Resulting In Fast Reset Loop Problem: Injection of a persistent Error #618 PAL call on the Intel® Itanium® Processor 9300 Series processor) provides the ability to change the window and threshold by
  • Intel BX80569Q9550 | Specification Update - Page 33
    increment their counter is extremely rare. Workaround: None at this time. Status: No Fix. 100. Problem: Intel® SMIPbox Does Not Drop Lanes Without Termination on Intel® QPI The Intel® QPI specification states that an alternate clock lane becomes a data lane after the fwd clock is locked to. All
  • Intel BX80569Q9550 | Specification Update - Page 34
    return value. To differentiate the two an implementation specific Unit Mask (umask-bits [19:16]) is needed. For retired umask is set to 5, for cycles umask is set to 2. Status: No Fix. 103. Problem: Intel® QPI State PHY_RESET / PHY_REINIT Not Supported The processor is designed to the
  • Intel BX80569Q9550 | Specification Update - Page 35
    No Fix. 106. Problem: Intel® QPI Dynamic Link Width Reduction May Result In Quarter and IIP = IVA, then the following criteria can be used to consider whether the problem has been hit. - Case (a): If IPSR.ic = Intel® Itanium® Processor 9300 Series and 9500 Series Specification Update 35 November 2012
  • Intel BX80569Q9550 | Specification Update - Page 36
    training. Alternatively to maintain Intel® QPI Alternate clock enabled, use 16-b rolling CRC and quarter-width Intel® QPI as the failover link width via PQ_CSR_PHWCI. This mitigates this issue which occurs in alternate clock mode. Status: No Fix. 111. Problem: Intel® QPI Alternate Clock Mode
  • Intel BX80569Q9550 | Specification Update - Page 37
    Intel® SMI Alternate clock is not supported on the processor. Workaround: Disable the Intel® SMI Alternate clock (PF_CSR_PLCR2.clk_failover_disable = 1). Status: No Fix. 115. Missing Thread After Error Reset Problem : None at this time. Intel can help diagnose if Minstate Memory is captured for any
  • Intel BX80569Q9550 | Specification Update - Page 38
    38 November 2012 Intel® Itanium® Processor 9300 Series and 9500 Series Specifiication Update
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Reference Number: 323169-010
Intel
®
Itanium
®
Processor 9300
Series and 9500 Series
Specification Update
November 2012