Intel BX80571E7500 Programming Manual

Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Manual

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  • Intel BX80571E7500 | Programming Manual - Page 1
    Intel® Xeon® Processor 7500 Series Uncore Programming Guide Reference Number: 323535-001 March 2010
  • Intel BX80571E7500 | Programming Manual - Page 2
    will vary depending on hardware and software configurations. Intel® Virtualization Technology-enabled BIOS and VMM applications are currently in development. 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and
  • Intel BX80571E7500 | Programming Manual - Page 3
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE CONTENTS CONTENTS CHAPTER 1 INTRODUCTION 1.1 INTRODUCTION 1-1 1.2 used in C-Box Events 2-16 2.3.4.3 The Queues 2-17 2.3.4.4 Detecting Performance Problems in the C-Box Pipeline 2-17 2.3.5 C-Box Events Ordered By Code
  • Intel BX80571E7500 | Programming Manual - Page 4
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE CONTENTS 2.5.4.2 2.5.4.3 2.5.5 2.5.6 2.6 2.6.1 2.6.1.1 2.6.1.2 2.6.1.3 2.6.1.4 MONITORING 2-95 Overview of the M-Box 2-95 Functional Overview 2-95 Intel ® 7500 Scalable Memory Buffer 2-96 M-Box Performance Monitoring Overview 2-96
  • Intel BX80571E7500 | Programming Manual - Page 5
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE FIGURES FIGURES Figure 1-1. Figure 2-1. Figure 2-2. Intel Xeon Processor 7500 Series Block Diagram 1-1 R-Box Block Diagram 2-72 Memory Controller Block Diagram 2-95
  • Intel BX80571E7500 | Programming Manual - Page 6
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE This page intentionally left blank FIGURES
  • Intel BX80571E7500 | Programming Manual - Page 7
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE TABLES TABLES Table 1-1. Table 1-2. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 2-10. Table 2-11. Table 2-12. Table 2-13. Table 2-14. Table 2-15.
  • Intel BX80571E7500 | Programming Manual - Page 8
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE TABLES Table 2-61. Table 2-62. Table 2-63. Table 2-64. Table 2-65. Table 2-66. Table 2-67. Table 2-68. Table 2-69. 128 Performance Monitor Events for W-Box Events 2-128 Intel® QuickPath Interconnect Packet Message Classes 2-130 Opcode
  • Intel BX80571E7500 | Programming Manual - Page 9
    PROGRAMMING GUIDE INTRODUCTION CHAPTER 1 INTRODUCTION 1.1 INTRODUCTION Figure 1-1 provides an Intel® Xeon® Processor 7500 Series block diagram. Figure 1-1. Intel Xeon Processor 7500 Series Block Diagram 1.2 Uncore PMU Overview The processor uncore performance monitoring is supported by
  • Intel BX80571E7500 | Programming Manual - Page 10
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE INTRODUCTION The general performance Table 1-1. Per-Box Performance Monitoring Capabilities # Boxes # Counters/ Generic Packet Match/ Box Counters? Mask Filters? Bit Width 8 6 Y N 48 2 4 Y Y 48 2 4 N Y 48 2 6 N
  • Intel BX80571E7500 | Programming Manual - Page 11
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE INTRODUCTION Box M-Box 1 M-Box 0 S-Box Counters S-Box 1 S-Box 0 B-Box Counters B-Box 1 B-Box 0 U-Box Counters U-Box W-Box Counters W-Box Table 1-2. Uncore Performance Monitoring MSRs MSR Addresses
  • Intel BX80571E7500 | Programming Manual - Page 12
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE • Section 2.8, "W-Box Performance Monitoring" • Section 2.9, "Packet Matching Reference" INTRODUCTION 1-4
  • Intel BX80571E7500 | Programming Manual - Page 13
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING CHAPTER 2 UNCORE PERFORMANCE MONITORING 2.1 Global capture them (i.e. typically selected by programming the .ev_sel bits although other bit fields may be involved). i.e. Set B_MSR_PMON_EVT_SEL3.ev_sel to
  • Intel BX80571E7500 | Programming Manual - Page 14
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE d) Enable counting at the box-level: Enable the freeze? Overflow bits are stored hierarchically within the Intel Xeon Processor 7500 Series uncore. First, software should read the U_MSR_PMON_GLOBAL_STATUS.ov_* bits to determine whether
  • Intel BX80571E7500 | Programming Manual - Page 15
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING a) Clear all uncore counters: Set U_MSR_PMON_GLOBAL_CTL.rst_all to 1. b) Clear all overflow bits. When an overflow bit is cleared, all bits that summarize that overflow (above in the hierarchy) will also be
  • Intel BX80571E7500 | Programming Manual - Page 16
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-2. U_MSR_PMON_GLOBAL_CTL Register - Field Definitions Field frz_all ig rst_all en_all ig pmi_core_sel Bits HW Reset Val Description 31 30 29 28 27:9 8:1 0 Disable uncore counting (by clearing .
  • Intel BX80571E7500 | Programming Manual - Page 17
    Intel Xeon Processor 7500 Series. It contains one counter which can be configured to capture a small set of events. 2.2.1 U-Box PMON Summary Table 2-5. U-Box Performance Monitoring MSRs MSR Name U_MSR_PMON_CTR U_MSR_PMON_EV_SEL Access MSR Address Size (bits) Description RW_RW 0x0C11 64
  • Intel BX80571E7500 | Programming Manual - Page 18
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING The U-Box performance monitor data register is 48b wide. A counter overflow occurs when a carry out bit from bit 47 is detected. Software can force all uncore counting to freeze after N events by preloading a
  • Intel BX80571E7500 | Programming Manual - Page 19
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-8. Performance Monitor Events Error 2.2.4 U-Box Performance Monitor Event List This section enumerates Intel Xeon Processor 7500 Series uncore performance monitoring events for the U-Box.
  • Intel BX80571E7500 | Programming Manual - Page 20
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE FATAL_ERR • Title: Fatal Errors • Category: U-Box Events • Event Code: 0x1E6, Max. Inc/Cyc: 1, • Definition: Number of fatal errors. IPIS_SENT • Title: Number Core IPIs Sent • Category: U-
  • Intel BX80571E7500 | Programming Manual - Page 21
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.3 C-Box Performance Monitoring 2.3.1 Overview of the C-Box For the Intel Xeon Processor the Intel Xeon Processor 7500 Series supports event how each C-Box's overflow bit is accumulated in the attached
  • Intel BX80571E7500 | Programming Manual - Page 22
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.3.3 C-BOX Performance Monitors Table 2-9. C-Box Performance Monitoring MSRs MSR Name Acces s MSR Addres s Size (bits ) Description CB7_CR_C_MSR_PMON_CTR_5 RW_R W 0xDFB 64 C-Box 7 PMON Counter 5
  • Intel BX80571E7500 | Programming Manual - Page 23
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSR Name Acces s MSR Addres s Size (bits ) Description CB5_CR_C_MSR_PMON_CTR_5 RW_R W 0xDBB 64 C-Box 5 PMON Counter 5 CB5_CR_C_MSR_PMON_EVT_SEL_5 RW_RO 0xDBA 64 C-Box 5 PMON Event Select 5
  • Intel BX80571E7500 | Programming Manual - Page 24
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSR Name Acces s MSR Addres s Size (bits ) Description CB6_CR_C_MSR_PMON_CTR_4 RW_R W 0xD79 64 C-Box 6 PMON Counter 4 CB6_CR_C_MSR_PMON_EVT_SEL_4 RW_RO 0xD78 64 C-Box 6 PMON Event Select 4
  • Intel BX80571E7500 | Programming Manual - Page 25
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSR Name Acces s MSR Addres s Size (bits ) Description CB4_CR_C_MSR_PMON_CTR_3 RW_R W 0xD37 64 C-Box 4 PMON Counter 3 CB4_CR_C_MSR_PMON_EVT_SEL_3 RW_RO 0xD36 64 C-Box 4 PMON Event Select 3
  • Intel BX80571E7500 | Programming Manual - Page 26
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING If an overflow is detected from one of the C-Box PMON registers, the corresponding bit in the _GLOBAL_STATUS.ov field will be set. To reset the overflow bits set in the _GLOBAL_STATUS.ov field, a user must
  • Intel BX80571E7500 | Programming Manual - Page 27
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-13. C_MSR_PMON_EVT_SEL{5-0} Register - Field Definitions Field ig rsv ig threshold invert en ig pmi_en ig edge_detect Bits HW Reset Val Description 63 62:61 60:50 31:24 23 22 21 20 19 18 0 Read
  • Intel BX80571E7500 | Programming Manual - Page 28
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.3.4 C-BOX Performance Monitoring Events ) are from the point of view of the LLC and cannot be associated with any specific core since all cores in the socket send their LLC transactions to all C-Boxes in
  • Intel BX80571E7500 | Programming Manual - Page 29
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE sustainable BW. That can be a sign of a performance problem that may be correctable with software tuning. One final useful to know if they are or are not localized to specific C-Boxes. 2.3.5 C-Box Events Ordered By Code Table 2-15
  • Intel BX80571E7500 | Programming Manual - Page 30
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-15. Performance Monitor Hits in LLC 2.3.6 C-Box Performance Monitor Event List This section enumerates Intel Xeon Processor 7500 Series uncore performance monitoring events for the C-Box. 2-18
  • Intel BX80571E7500 | Programming Manual - Page 31
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING ARB_LOSSES • Title: Arbiter Losses. • Category: Ring - Egress • Event Code: 0x0A, Max. Inc/Cyc: 7, • Definition: Number of Ring arbitration losses. A loss occurs when a
  • Intel BX80571E7500 | Programming Manual - Page 32
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING BOUNCES_C2P_AK • Title: C2P AK Event Code: 0x04, Max. Inc/Cyc: 1, • Definition: Number of C-Box snoops of a processor's cache that bounced on the IV ring. BOUNCES_P2C_AD • Title: P2C AD Bounces • Category:
  • Intel BX80571E7500 | Programming Manual - Page 33
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING EGRESS_BYPASS_WINS • Title: Egress Bypass Wins • Category: Local - Egress • Event Code: 0x0C, Max. Inc/Cyc: 7, • Definition: Number of times a ring egress bypass was
  • Intel BX80571E7500 | Programming Manual - Page 34
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Extension F ALL umask [15:8] Description b00001xxx Forward (S with right to Forward on snoop) b00001111 All hits (to any cacheline state) LLC_MISSES • Title:
  • Intel BX80571E7500 | Programming Manual - Page 35
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MAF_ACK • Title: MAF ACK • Category: Local - MAF • b00000000 (*nothing will be counted*) bxxxxxxx1 An incoming local processor RD/WR or remote Intel QPI snoop request that required a MAF entry was delayed
  • Intel BX80571E7500 | Programming Manual - Page 36
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Extension EGRESS_FULL umask [15:8] Description bxxxxxx1x Some incoming message to the LLC that needed to generate a response message for transmission onto the
  • Intel BX80571E7500 | Programming Manual - Page 37
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING OCCUPANCY_RWRF • Title: RWRF Occupancy of messages sunk from the ring at the C-Box that were sent by one of the local processors. • NOTE: Each sink represents the transfer of 32 bytes, or 2 sinks per cache
  • Intel BX80571E7500 | Programming Manual - Page 38
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING SINKS_S2C • Title: S2C Sinks • Category: Ring - WIR • Event Code: 0x07, Max. Inc/Cyc: 3, • Definition: Number of messages sunk from the ring at
  • Intel BX80571E7500 | Programming Manual - Page 39
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING SNPS • Title: Snoops to LLC • Category: Local - CC • Event Code: 0x27, Max. Inc/Cyc: 1, • Definition: Number of Intel QPI snoops seen by the LLC. • NOTE: Subtract CACHE_CHAR_QUAL.ANY_HIT from this event to
  • Intel BX80571E7500 | Programming Manual - Page 40
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING TRANS_IRQ • Title: IRQ Transactions • Category: Queue Occupancy • Event Code: 0x19, Max. Inc/Cyc: 1, • Definition: Number of processor RD and/or WR requests to the LLC that entered the Ingress Response Queue.
  • Intel BX80571E7500 | Programming Manual - Page 41
    Performance Monitoring Overview Each of the two B-Boxes in the Intel Xeon Processor 7500 Series supports event monitoring through four 48-bit wide counters (BBx_CR_B_MSR_PERF_CNT{3:0}). Each of these four counters is dedicated to observe a specific set of events as specified in its control register
  • Intel BX80571E7500 | Programming Manual - Page 42
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.4.3 B-BOX Performance Monitors Table 2-16. B-Box Performance Monitoring MSRs MSR Name BB1_CR_B_MSR_MASK BB1_CR_B_MSR_MATCH BB0_CR_B_MSR_MASK BB0_CR_B_MSR_MATCH Access MSR Address Size (bits)
  • Intel BX80571E7500 | Programming Manual - Page 43
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-17. B_MSR_PMON_GLOBAL_CTL Register - Field Definitions Field ctr_en Bits HW Reset Val Description 3:0 0 Must be set to enable each B-Box counter (bit 0 to enable ctr0, etc) NOTE: U-Box enable
  • Intel BX80571E7500 | Programming Manual - Page 44
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-20. B_MSR_PMON_EVT_SEL{3-0} Register - Field Definitions Field ig rsv ig rsv ig pmi_en ig ev_sel en Bits Note: Refer to Table 2-103, "Intel® QuickPath Interconnect Packet Message Classes" and
  • Intel BX80571E7500 | Programming Manual - Page 45
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-22. B_MSR_MATCH_REG Register - Field Definitions Field opc_out opc_in msg_out MC Bits HW Reset Val Description 59:56 55:52 51:48 12:9 0 Match to this outgoing opcode 0 Match to this incoming
  • Intel BX80571E7500 | Programming Manual - Page 46
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING • SNPOQ (SNP Output Queue a NonSnpWrData(Ptl) needs to be sent to the mirror slave and VN1 DRS channel or Intel QPI output resources are unavailable. • MHOMOQ (Mirror HOM Output Queue) 256-entry - Request
  • Intel BX80571E7500 | Programming Manual - Page 47
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-24. Performance Monitor Events for B-Box Events Symbol Name Event Max Code Inc/Cyc Description Counter 0 Events MSG_ADDR_IN_MATCH OPCODE_ADDR_IN_MATCH MSG_OPCODE_ADDR_IN_MATCH TF_OCCUPANCY_ALL
  • Intel BX80571E7500 | Programming Manual - Page 48
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-24. Performance Monitor Events for B-Box Events Symbol Name IMT_NE_CYCLES Counter 3 Events EARLY_ACK IMT_PREALLOC DEMAND_FETCH IMPLICIT_WBS COHQ_IMT_ALLOC_WAIT SBOX_VN0_UNAVAIL RBOX_VNA_UNAVAIL
  • Intel BX80571E7500 | Programming Manual - Page 49
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING COHQ_IMT_ALLOC_WAIT • Title: COHQ IMT Allocation Wait • Category: ARB Queues • Event Code: 0x13, Max. Inc/Cyc: 1, PERF_CTL: 3, • Definition: Cycles Coherence Queue Waiting on
  • Intel BX80571E7500 | Programming Manual - Page 50
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING IMT_FULL • Title: IMT Full • with IMT_VALID_OCCUPANCY) be used to derive average IMT latency or latency for specific flavors of inserts. IMT_INSERTS_IOH_INVITOE • Title: IMT IOH InvItoE Inserts • Category
  • Intel BX80571E7500 | Programming Manual - Page 51
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING IMT_INSERTS_IOH_WR • Title: IMT (along with IMT_VALID_OCCUPANCY) be used to derive average IMT latency or latency for specific flavors of inserts. IMT_INSERTS_NON_IOH • Title: IMT Non-IOH Inserts • Category:
  • Intel BX80571E7500 | Programming Manual - Page 52
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING IMT_INSERTS_RD • Title: IMT Read (along with IMT_VALID_OCCUPANCY) be used to derive average IMT latency or latency for specific flavors of inserts. IMT_NE_CYCLES • Title: IMT Non-Empty Cycles • Category: In
  • Intel BX80571E7500 | Programming Manual - Page 53
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSG_IN_MATCH • Title: Message In Match • Category: Mask/Match • Event Code: 0x01, Max. Inc/Cyc: 1, PERF_CTL: 1, • Definition: Message Class Match at B-Box Input.
  • Intel BX80571E7500 | Programming Manual - Page 54
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING OPCODE_IN_MATCH • Title: Opcode In Match • Category: Mask/Match • Event Code: 0x03, Max. Inc/Cyc: 1, PERF_CTL: 1, • Definition: Opcode Match at B-Box Input. Use
  • Intel BX80571E7500 | Programming Manual - Page 55
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING TF_INVITOE • Title: TF Occupancy - InvItoEs • Category: Tracker File • Event Code: 0x06, Max. Inc/Cyc: 1, PERF_CTL: 0, • Definition: Tracker File occupancy for InvItoE requests.
  • Intel BX80571E7500 | Programming Manual - Page 56
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING TF_WR • Title: TF Occupancy - Writes • Category: Tracker File • Event Code: 0x05, Max. Inc/Cyc: 1, PERF_CTL: 0, • Definition: Tracker File occupancy for write requests.
  • Intel BX80571E7500 | Programming Manual - Page 57
    Intel Xeon Processor 7500 Series supports event monitoring through 4 48b wide counters (S_MSR_PMON_CTR/CTL{3:0}). Each of these four counters can be programmed to count any S-Box event. the S-Box counters can increment by a maximum of 64 Box performance counter, the overflow bit is set at the box
  • Intel BX80571E7500 | Programming Manual - Page 58
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSR Name Access MSR Address Size (bits) Description SS0_CR_S_MSR_MASK SS0_CR_S_MSR_MATCH SS0_CR_S_MSR_MM_CFG RW_RO 0x0E4A 64 S-Box 0 Enable Mask Register RW_RO 0x0E49 64 S-Box 0 Enable Match Register
  • Intel BX80571E7500 | Programming Manual - Page 59
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Field ig ov_r ov_s ig ov_mb ig ov_c_l ig ov_c_r Table 2-26. S_MSR_PMON_SUMMARY Register Fields Bits HW Reset Val Description 63:20 19 18 17 16 15:3 2 1 0 Read zero; writes ignored. 0 Overflow in R Box
  • Intel BX80571E7500 | Programming Manual - Page 60
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Field clr_ov Table 2-29. S_MSR_PMON_OVF_CTRL Register Fields Bits HW Reset Val Description 3:0 0 Writing '1' to bit in filed causes corresponding bit reset_occ_cnt ig umask ev_sel Bits HW Reset Val
  • Intel BX80571E7500 | Programming Manual - Page 61
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING The S-Box performance monitor data registers are 48b wide. A counter overflow occurs when a carry out bit from bit 47 is detected. Software can force all uncore counting to freeze after N events by preloading
  • Intel BX80571E7500 | Programming Manual - Page 62
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Field resp opc mc addr hnid Table 2-33. S_MSR_MATCH Register - Field Definitions Bits HW Reset Val Description 63:59 0 Match if returning data is in b1xxxx - 'F' state. bx1xxx - 'S' state bxx1xx - 'E'
  • Intel BX80571E7500 | Programming Manual - Page 63
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Field ig addr hnid Table 2-35. S_MSR_MASK Register - Field Definitions Bits HW Reset Val Description 62:39 38:1 0 Read zero; writes ignored. 0 Mask PA address bits [43:6]. For each mask bit that is set,
  • Intel BX80571E7500 | Programming Manual - Page 64
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-36. S-Box Data Structure Occupancy Events Structure/Event Name Subev Max Insta Entries nces Description/Comment System Bound HOM Message RBOX 64 Queue TO_R_B_HOM_MSGQ_OCCUPANCY B-Box 64 ALL
  • Intel BX80571E7500 | Programming Manual - Page 65
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Message Class Ring Bound System Bound NCS Message Queue Full 1 Cycles System Bound NCS Message Queue Not Empty 64 System Bound NCS Message Queue Occupancy 1 Cycles Ring Bound SNP Message Queue Full
  • Intel BX80571E7500 | Programming Manual - Page 66
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-37. Performance Monitor Events for S-Box Events Symbol Name TO_RING_NCB_MSGQ_CYCLES_NE TO_RING_NCS_MSGQ_CYCLES_NE TO_RING_MSGQ_OCCUPANCY TO_RING_NDR_MSGQ_CYCLES_FULL TO_RING_NDR_MSGQ_CYCLES_NE
  • Intel BX80571E7500 | Programming Manual - Page 67
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-37. Performance Monitor Events for S-Box Events Symbol Name NO_CREDIT_HOM NO_CREDIT_SNP NO_CREDIT_DRS NO_CREDIT_NCS NO_CREDIT_NCB NO_CREDIT_NDR NO_CREDIT_VNA NO_CREDIT_AD NO_CREDIT_AK NO_CREDIT_BL
  • Intel BX80571E7500 | Programming Manual - Page 68
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING EGRESS_ARB_LOSSES • Title: Egress ARB Losses • Category: Ring Bound Credits • Event Code: 0x42, Max. Inc/Cyc: 1, • Definition: Egress Arbitration Losses. • NOTE: Enabling multiple
  • Intel BX80571E7500 | Programming Manual - Page 69
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING EGRESS_BYPASS • Title: Egress Bypass • Category: Ring Bound Enhancement • Event Code: 0x40, Max. Inc/Cyc: 1, • Definition: Egress Bypass optimization utilized. • NOTE: Enabling multiple
  • Intel BX80571E7500 | Programming Manual - Page 70
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING FLITS_SENT_DRS • Title: DRS Flits Sent to System • Category: System Bound Transmission • Event Code: 0x65, Max. Inc/Cyc: 1, • Definition: Number of data response
  • Intel BX80571E7500 | Programming Manual - Page 71
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING NO_CREDIT_HOM • Title: HOM Credit Unavailable • Category: System Bound Credits • Event Code: 0x80, Max. Inc/Cyc: 1, • Definition: Number of times the S-Box has a
  • Intel BX80571E7500 | Programming Manual - Page 72
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING NO_CREDIT_VNA • Title: VNA Credit Unavailable • Category: System Bound Transmission • Event Code: 0x86, Max. Inc/Cyc: 1, • Definition: Number of times the S-Box has
  • Intel BX80571E7500 | Programming Manual - Page 73
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING PKTS_RCVD_SNP • Title: SNP Packets Received from System • Category: Ring Bound Transmission • Event Code: 0x71, Max. Inc/Cyc: 1, • Definition: Number of snoop packets
  • Intel BX80571E7500 | Programming Manual - Page 74
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING CBOX2_6 CBOX3_7 bx1xx b1xxx C-Boxes 2 and 6 C-Boxes 3 and 7 PKTS_SENT_NCS • Title: NCS Packets Sent to System • Category: System Bound Transmission • Event Code: 0x66,
  • Intel BX80571E7500 | Programming Manual - Page 75
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING RBOX_SNP_BYPASS • Title: R-Box SNP Bypass • Category: System Bound Enhancement • Event Code: 0x51, Max. Inc/Cyc: 1, • Definition: R-Box SNP bypass optimization utilized. When
  • Intel BX80571E7500 | Programming Manual - Page 76
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING TO_RING_B2S_MSGQ_OCCUPANCY • Title: Ring Bound B2S Message Queue Occupancy • Category: Ring Bound Queue • Event in which the header buffer, containing NDR messages on their way to the Ring, is full. 2-64
  • Intel BX80571E7500 | Programming Manual - Page 77
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING TO_RING_NDR_MSGQ_CYCLES_NE • Title: Cycles Ring Bound NDR Message Queue Not Empty • Category: Ring Bound Queue • Event Code: 0x28, Max. Inc/Cyc: 1, • Definition: Number
  • Intel BX80571E7500 | Programming Manual - Page 78
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING TO_R_DRS_MSGQ_CYCLES_FULL • Title: Cycles System Bound DRS Message Queue Full. • Category: System Bound Queue • Event Code: 0x0E, Max. Inc/Cyc: 1, • Definition: Number of
  • Intel BX80571E7500 | Programming Manual - Page 79
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING CBOX3_7 ALL b1xxx b1111 CBOX 3 and total number of entries in the R-Box and B-Box Home header buffers is equal to 64. Extension --RBOX BBOX RBBOX umask [15:8] b00 b01 b10 b11 Description (*nothing will
  • Intel BX80571E7500 | Programming Manual - Page 80
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING TO_R_NCB_MSGQ_CYCLES_FULL • Title: Cycles System Bound NCB Message Queue Full. • Category: System Bound Queue • Event Code: 0x11, Max. Inc/Cyc: 1, • Definition: Number of
  • Intel BX80571E7500 | Programming Manual - Page 81
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING CBOX3_7 ALL b1xxx b1111 CBOX 3 and 7 All C-Boxes TO_R_NCS_MSGQ_CYCLES_FULL • Title: Cycles System Bound NCS Message Queue Full. • Category: System Bound Queue • Event
  • Intel BX80571E7500 | Programming Manual - Page 82
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING CBOX1_5 CBOX2_6 CBOX3_7 ALL bxx1x bx1xx b1xxx b1111 CBOX 1 and 5 CBOX 2 and 6 CBOX 3 and 7 All C-Boxes TO_R_NDR_MSGQ_CYCLES_FULL • Title: Cycles System Bound NDR
  • Intel BX80571E7500 | Programming Manual - Page 83
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING TO_R_SNP_MSGQ_CYCLES_FULL • Title: Cycles System Bound SNP Message Queue Full • Category: System Bound Queue • Event Code: 0x08, Max. Inc/Cyc: 1, • Definition: Number of
  • Intel BX80571E7500 | Programming Manual - Page 84
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.6 R-Box Performance Monitoring 2.6.1 Overview of the R-Box The Crossbar Router (R-Box) is a 8 port switch/router implementing the Intel Table (ET). R-Box PMU supports performance monitoring in these two
  • Intel BX80571E7500 | Programming Manual - Page 85
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.6.1.3 R-Box Output Port The R-Box output port acts as a virtual supports up to three virtual networks (VN0, VN1, and VNA) as defined by the Intel® QuickPath Interconnect Specification packets serviced (
  • Intel BX80571E7500 | Programming Manual - Page 86
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE bits) Description RW_NA 0x0E9E 64 R-Box Port 7 Mask 2 RW_NA 0x0E9D 64 R-Box Port 7 Match 2 RW_NA 0x0E9C 64 R-Box Port 7 Mask/Match Config 2 RW_NA 0x0E8E 64 R-Box Port 7 Mask 1 RW_NA 0x0E8D 64 R-Box Port 7 Match 1 RW_NA 0x0E8C 64
  • Intel BX80571E7500 | Programming Manual - Page 87
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSR Name R_MSR_PORT5_XBR_SET1_MASK R_MSR_PORT5_XBR_SET1_MATCH R_MSR_PORT5_XBR_SET1_MM_CFG Access MSR Addres s Size (bits) Description RW_NA 0x0E86 64 R-Box Port 5 Mask 1 RW_NA 0x0E85 64 R-Box Port 5
  • Intel BX80571E7500 | Programming Manual - Page 88
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE bits) Description RW_RW 0x0E3B 64 R-Box PMON Counter 13 RW_NA 0x0E3A 64 R-Box PMON Control 13 RW_RW 0x0E39 64 R-Box PMON Counter 12 RW_NA 0x0E38 64 R-Box PMON Control 12 RW_RW 0x0E37 64 R-Box PMON Counter 11 RW_NA 0x0E36 64
  • Intel BX80571E7500 | Programming Manual - Page 89
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSR Name R_MSR_PMON_CTR1 R_MSR_PMON_CTL1 R_MSR_PMON_CTR0 R_MSR_PMON_CTL0 Access MSR Addres s Size (bits) Description RW_RW 0x0E13 64 R-Box PMON Counter 1 RW_NA 0x0E12 64 R-Box PMON Control 1 RW_RW
  • Intel BX80571E7500 | Programming Manual - Page 90
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.6.3.2 R-Box Box Level PMON state The following registers represent the state governing all box-level PMUs in the R-Box. The _GLOBAL_CTL register contains the bits used to enable monitoring. It is
  • Intel BX80571E7500 | Programming Manual - Page 91
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-44. R_MSR_PMON_CTL{15-0} Register - Field Definitions Field ig rsv ig pmi_en ev_sel Bits HW Reset Val Description 63 62:61 60:7 6 5:1 0 Read zero; writes ignored. (?) 0 Reserved; Must write to 0
  • Intel BX80571E7500 | Programming Manual - Page 92
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-45. R_MSR_PMON_CTL{15-8} Event Select Name PORT4_IPERF0 PORT4_IPERF1 PORT4_QLX0 PORT4_QLX1 PORT4_XBAR_MM1 PORT4_XBAR_MM2 PORT5_IPERF0 PORT5_IPERF1 PORT5_QLX0 PORT5_QLX1 PORT5_XBAR_MM1 PORT5_XBAR_MM2
  • Intel BX80571E7500 | Programming Manual - Page 93
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING R-Box performance monitor data registers are 48b wide. A counter overflow occurs when a carry out bit from bit 47 is detected. Software can force all uncore counting to freeze after N events by preloading a
  • Intel BX80571E7500 | Programming Manual - Page 94
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.6.3.4 R-Box IPERF of 2) Field FLT_SENT NULL_IDLE RETRYQ_OV RETRYQ_NE OUTQ_OV OUTQ_NE RCVD_SPEC_FLT RCVD_ERR_FLT ig MC_ROLL_ALLOC MC Bits HW Reset Val Description 31 30 29 28 27 26 25 24 23:22 21
  • Intel BX80571E7500 | Programming Manual - Page 95
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-48. R_MSR_PORT{7-0}_IPERF_CFG{1-0} Registers (Sheet 2 of 2) Field IQA_READ_OK NEW_PVN Bits HW Reset Val Description 8 0x0 Bid wins arbitration. Read flit from IQA and drains to XBAR. 7:6 0x0
  • Intel BX80571E7500 | Programming Manual - Page 96
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Field ev1_type ev0_sub ev0_cls ev0_type Table 2-49. R_MSR_PORT{7-0}_QLX_CFG Register Fields (Sheet 2 of 2) Bits that allow a user to filter packet traffic serviced (crossing from an input port to an output
  • Intel BX80571E7500 | Programming Manual - Page 97
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING To use the match/mask facility : a) Set the MM_CFG (see Table 2-50, "R_MSR_PORT{7-0}_XBR_SET{2-1}_MM_CFG Registers") .dis field (bit 63) to 0 and .mm_trig_en (bit 21) to 1. NOTE: In order to monitor packet
  • Intel BX80571E7500 | Programming Manual - Page 98
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Field MC OPC VNW --- Table 2-51. R_MSR_PORT{7-0}_XBR_SET{2-1}_MATCH Registers (Sheet 2 of 2) Bits opcodes that may be filtered per message class. 4:3 0x0 Virtual Network b00 - VN0 b01 - VN1 b1x - VNA
  • Intel BX80571E7500 | Programming Manual - Page 99
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE 9 flits in length. A 9 flit NCB message contains a full 64 byte cache line. 0x1F00 Any Non-Coherent Bypass message that is 11 message. NCB interrupt messages are 11 flits in length. NOTE: Bits 71:16 of the match/mask must be 0 in order
  • Intel BX80571E7500 | Programming Manual - Page 100
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 0 Table 2-54. Performance Xeon Processor 7500 Series uncore performance monitoring events for the R-Box. ALLOC_TO_ARB • Title: Transactions allocated to ARB • Category: RIX • [Bit(s)] Value: See Note, Max.
  • Intel BX80571E7500 | Programming Manual - Page 101
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Extension --NCB NCS DRS_VN01 NDR SNP HOM_VN0 HOM_VN1 ALL Table 2-55. Unit Masks for ALLOC_TO_ARB IPERF Bit Table 2-56. Unit Masks for EOT_DEPTH_ACC IPERF Bit Values [20:17] Description b0000 (*nothing
  • Intel BX80571E7500 | Programming Manual - Page 102
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING EOT_OCCUPANCY • Title: EOT Occupancy • Category: RIX • [Bit(s)] Value: [21]0x0, Max. Inc/Cyc: 1, • Definition: Used with MC field. Report a rolling count whenever a 7b counter (count == 128) over- flows for
  • Intel BX80571E7500 | Programming Manual - Page 103
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING GLOBAL_ARB_BID_FAIL • Title: Failed Global ARB Bids • Category: QLX • [Bit(s)] Value: [3:0]0x5, Max. Inc/Cyc: 1, • Definition: Number of bids for output port that were rejected at the global ARB. Extension
  • Intel BX80571E7500 | Programming Manual - Page 104
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING NEW_PACKETS_RECV • Title: New Packets Received by Port • Category: RIX • [Bit(s)] Value: see table, Max. Inc/Cyc: 1, • Definition: Counts new packets received according to the Virtual IPERF Bit Values
  • Intel BX80571E7500 | Programming Manual - Page 105
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING OUTPUTQ_NE • Title: Output Queue Not Empty • Category: RIX • [Bit(s)] Value: [26]0x1, Max. Inc/Cyc: 1, • Definition: Output Queue Not Empty in this Output Port. OUTPUTQ_OVFL • Title: Output Queue Overflowed •
  • Intel BX80571E7500 | Programming Manual - Page 106
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING RETRYQ_NE • Title: Retry Queue Not Empty • Category: RIX • [Bit(s)] Value: [28]0x1, Max. Inc/Cyc: 1, • Definition: Retry Queue Not Empty in this Output Port. RETRYQ_OV • Title: Retry Queue Overflowed •
  • Intel BX80571E7500 | Programming Manual - Page 107
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.7 M-Box Performance Monitoring 2.7.1 Overview of the M-Box The memory controller interfaces to the Intel® 7500 Scalable Memory Buffers and translates read and write commands into specific Intel®
  • Intel BX80571E7500 | Programming Manual - Page 108
    7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.7.2.1 Intel ® 7500 Scalable Memory Buffer The Intel Xeon Processor 7500 Series supports Intel® 7500 Scalable Memory Buffers on the Intel® SMI channels. • Intel SMI protocol and signalling includes support for the following
  • Intel BX80571E7500 | Programming Manual - Page 109
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING For instance, to count ( and Unfreeze If an overflow is detected from an M-Box performance counter, the overflow bit is set at the box level (M_MSR_PMON_GLOBAL_STATUS.ov), and forwarded up the chain towards
  • Intel BX80571E7500 | Programming Manual - Page 110
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.7.4 M-BOX Performance Monitors Table 2-63. M-Box Performance Monitoring MSRs MSR Name MB1_CR_M_MSR_PMU_ADDR_MASK MB1_CR_M_MSR_PMU_ADDR_MATCH MB1_CR_M_MSR_PMU_MM_CFG Access MSR Address Size (bits)
  • Intel BX80571E7500 | Programming Manual - Page 111
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE bits) Description RW_RW 0x0CB9 64 M-Box 0 PMON Counter 4 RW_RW 0x0CB8 64 M-Box 0 PMON Control 4 RW_RW 0x0CB7 64 M-Box 0 PMON Counter 3 RW_RW 0x0CB6 64 M-Box 0 PMON Control 3 RW_RW 0x0CB5 64 M-Box 0 PMON Counter 2 RW_RW 0x0CB4 64
  • Intel BX80571E7500 | Programming Manual - Page 112
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Field ctr_en Table 2-64. M_MSR_PERF_GLOBAL_CTL Register Fields Bits HW Reset Val Description 5:0 0 Must be set to enable each MBOX 0 counter (bit 0 to enable ctr0, etc) NOTE: U-Box enable and per
  • Intel BX80571E7500 | Programming Manual - Page 113
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-67. M_MSR_PMU_CNT_CTL{5-0} Register - Field Definitions Field ig rsv ig rsv set_flag_sel rsv inc_sel rsv flag_mode wrap_mode storage_mode count_mode pmi_en en Bits HW Reset Val Description 63 62:
  • Intel BX80571E7500 | Programming Manual - Page 114
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-69. M_MSR_PMU_TIMESTAMP_UNIT Register - Field Definitions Field timestamp Bits 71. M_MSR_PMU_ADDR_MATCH Register - Field Definitions Field ig address Bits HW Reset Val Description 63:34 33:0 0
  • Intel BX80571E7500 | Programming Manual - Page 115
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Original B-Box transaction's FVID sent from DSP during subcommand execution where the appropriate subcommand information is accessed to compose the Intel contains bits to specify subevents of the DSP_FILL event
  • Intel BX80571E7500 | Programming Manual - Page 116
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-73. M_MSR_PMU_DSP Register - Field Definitions Field ig wrq_empty rdq_empty wrq_full rdq_full lat_cnt_en fvid Bits HW Reset Val Description 63:11 10 9 8 7 6 5:0 0 Read zero; writes ignored. (?)
  • Intel BX80571E7500 | Programming Manual - Page 117
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING The MAP subcontrol register contains bits to specify subevents for BCMD_SCHEDQ_OCCUPANCY (by BBox command type). Table 2-75. M_MSR_PMU_MAP Register - Field Definitions Field ig set_patrol_req sel_map_ev3
  • Intel BX80571E7500 | Programming Manual - Page 118
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-77. TRP_PT_{ temperature trip point. Below the low temperature trip point. The PGT subcontrol register contains bits to specify subevents for CYCLES_PGT_STATE (time spent in open or closed state) and
  • Intel BX80571E7500 | Programming Manual - Page 119
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-79. M_MSR_PMU_PLD Register - Field Definitions Field ig pld_trig_sel addr_match1 dram_cmd rtry_sngl_fvid fvid cmd Bits HW Reset Val Reset Type 31:14 15:14 13 12:8 Reads 0; writes ignored. 0 When
  • Intel BX80571E7500 | Programming Manual - Page 120
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-80. M_MSR_PMU_ZDP_CTL_FVC Register - Field Definitions Field ig pbox_init_err evnt3 evnt2 evnt1 evnt0 resp bcmd fvid Bits HW Reset Val Reset Type 31:24 23 22:20 19:17 16:14 13:11 10:8 7:5 4:0
  • Intel BX80571E7500 | Programming Manual - Page 121
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-82. M_MSR_PMU_ZDP_CTL_FVC.RESP Encodings Name spr_uncor_resp Reserved spr_ack_resp spec_ack_resp uncor_resp corr_resp retry_resp ack_resp Value Description 0b111 Uncorrectable response for command
  • Intel BX80571E7500 | Programming Manual - Page 122
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING - Auto page closes. - Open-page to closed-page policy transitions. As well as length of time spent in each policy. - Starvation event
  • Intel BX80571E7500 | Programming Manual - Page 123
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-84. Performance Monitor Events for Occupancy 2.7.7 M-Box Performance Monitor Event List This section enumerates Intel Xeon Processor 7500 Series uncore performance monitoring events for the M-Box.
  • Intel BX80571E7500 | Programming Manual - Page 124
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING CYCLES_PGT_STATE • Title: Time in Page Table State the PLD Dep bits [13,7,0] are also set to 0 Extension ALL ILLEGAL PREALL PLD Dep Bits [0]0x0 [12:8]0x0 [12:8]0x1 ISS Dep Bits Description Advance counter
  • Intel BX80571E7500 | Programming Manual - Page 125
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Extension PREALL. 12:8]0x5 && [0]0x1 [12:8]0x6 [12:8]0x6 && [0]0x1 [12:8]0x6 && [0]0x1 ISS Dep Bits [9:7]0x0 [9:7]0x1 [9:7]0x2 [9:7]0x2 [9:7]0x0 [9:7]0x1 [9:7]0x2 [9:7]0x2 [9:7]0x0 [9:7]0x1 [9:7]0x2 [9:7]0x3
  • Intel BX80571E7500 | Programming Manual - Page 126
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Extension CAS_WR_CLS.WRPRIO CAS_WR_CLS.ADAPTIVE MRS RFR ENSR EXSR NOP TRKL PRE SYNC CKE_HI CKE_LO SOFT_RST WR_CFG RD_CFG ZQCAL ALL.TRDOFF ALL.RDPRIO ALL.WRPRIO ALL.ADAPT PLD Dep Bits [12:8]0x6 && [0]0x1 [12
  • Intel BX80571E7500 | Programming Manual - Page 127
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING FVC_EVx monitored. However, the bcmd_match and resp_match subevents depend on the setting of additional bits in the FVC register (11:9 and 8:5 respectively). Therefore, only ONE FVC_EVx.bcmd_match
  • Intel BX80571E7500 | Programming Manual - Page 128
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Extension monitored. However, the bcmd_match and resp_match subevents depend on the setting of additional bits in the FVC register (11:9 and 8:5 respectively). Therefore, only ONE FVC_EVx.bcmd_match
  • Intel BX80571E7500 | Programming Manual - Page 129
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Extension BBOX_CMDS monitored. However, the bcmd_match and resp_match subevents depend on the setting of additional bits in the FVC register (11:9 and 8:5 respectively). Therefore, only ONE FVC_EVx.bcmd_match
  • Intel BX80571E7500 | Programming Manual - Page 130
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Extension BBOX_RSP.COR BBOX_RSP.UNCOR to misbehaving DIMM during sparing Select Intel SMI Northbound debug event bits from Intel SMI status frames as returned from the Intel 7500 Scalable Memory Buffers. Used
  • Intel BX80571E7500 | Programming Manual - Page 131
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING BCMD_SCHEDQ_OCCUPANCY • Title: B-Box Command Scheduler Queue Occupancy • Category: Cycle Events • Event Code: [21:19]0x06 && [7]0x1, Max. Inc/Cyc: 1, • Definition: Counts the
  • Intel BX80571E7500 | Programming Manual - Page 132
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING PAGE_MISS • Title: Page Table • Definition: Counts PGT Related Page Table Events. Extension OPN2CLS CLS2OPN PGT Bits[0] 0x1 0x0 Description Advance counter when an open-to-closed page mode transition
  • Intel BX80571E7500 | Programming Manual - Page 133
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING RETRY_MFULL • Title: Retry MFull • trip point (rising) is crossed in the "down" direction for DIMM #? NOTE: THR Bits [6:4] must be programmed with the DIMM # Advance the counter when the above mid temp
  • Intel BX80571E7500 | Programming Manual - Page 134
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Extension DIMM{n}.GT_LO DIMM{n}.LT_LO THR Bits [10:9],[3] Description 0x1,0x0 0x0,0x0 Advance the counter when the above low temp, but below mid temp thermal trip point is crossed in the "
  • Intel BX80571E7500 | Programming Manual - Page 135
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING TT_CMD_CONFLICT • Title: Thermal Throttling Command Conflicts • Category: Thermal Throttle • Event Code: 0x19, Max. Inc/Cyc: 1, • Definition: Count command conflicts due to thermal
  • Intel BX80571E7500 | Programming Manual - Page 136
    GUIDE UNCORE PERFORMANCE MONITORING 2.8 W-Box Performance Monitoring 2.8.1 Overview of the W-Box The W-Box is the primary Power Controller for the Intel Xeon Processor 7500 Series. 2.8.2 W-Box Performance Monitoring Overview The W-Box supports event monitoring through four 48-bit
  • Intel BX80571E7500 | Programming Manual - Page 137
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.8.3 W-BOX Performance Monitors Table 2-94. W-Box Performance Monitoring MSRs MSR Name W_MSR_PMON_FIXED_CTR_CTL W_MSR_PMON_FIXED_CTR Access MSR Address Size (bits) Description RW_RW 0x395 64 W-Box
  • Intel BX80571E7500 | Programming Manual - Page 138
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-96. W_MSR_PMON_GLOBAL_STATUS Register Fields Field ov_fixed ig ov Bits HW Reset Val Description 31 30:4 3:0 0 If an overflow is detected from the WBOX PMON fixed counter, this bit will be set. 0
  • Intel BX80571E7500 | Programming Manual - Page 139
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-98. W_MSR_PMON_EVT_SEL_{3-0} Register - Field Definitions Field ig rsv ig rsv ig thresh invert en ig pmi_en ig edge_detect ig umask ev_sel Bits HW Reset Val Description 63 62:61 60:51 50 49:32 31
  • Intel BX80571E7500 | Programming Manual - Page 140
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-100. W_MSR_PMON_CTR_{3-0} Register - Field Definitions Field event_count Bits HW Reset Val Description 47:0 0 48-bit performance event counter Table 2-101. W_MSR_PMON_FIXED_CTR Register - Field
  • Intel BX80571E7500 | Programming Manual - Page 141
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING C_CYCLES_TURBO • Title: Core in C0 at Turbo • Category: W-Box Events • Event Code: 0x04, Max. Inc/Cyc: 1, • Definition: Selected core is in C0
  • Intel BX80571E7500 | Programming Manual - Page 142
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.9 Packet Matching Reference In Opcode fields, have been summarized in the following tables. Table 2-103. Intel® QuickPath Interconnect Packet Message Classes Code b0000 b0001 b0010 b0011 b0100 --b1100
  • Intel BX80571E7500 | Programming Manual - Page 143
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-104. Opcode Match by Message Class Opc HOM0 0000 RdCur 0001 RdCode 0010 RdData 0011 NonSnpRd 0100 RdInvOwn 0101 InvXtoI 0110
  • Intel BX80571E7500 | Programming Manual - Page 144
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table , Complete NOTE: Set RDS field to specify which state is to be measured. - Intel Xeon Processor 7500 Series supports getting data in E, F or I state Data Response in (FEIMS) state, Force Acknowledge
  • Intel BX80571E7500 | Programming Manual - Page 145
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Name NcIOWr NcMsgB NcMsgS NcP2PB NcP2PS NcRd NcRdPtl NcWr NcWrPtl is left with line in S-state Snoop Code (get data in F or S state) - Intel Xeon Processor 7500 Series supports getting data in F state 2-133
  • Intel BX80571E7500 | Programming Manual - Page 146
    INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Name SnpCur get data in I state Snoop Data (get data in E, F or S state) - Intel Xeon Processor 7500 Series supports getting data in E or F state Snoop Invalidate to E state. To invalidate peer caching agent
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Intel® Xeon® Processor 7500 Series
Uncore Programming Guide
Reference Number: 323535-001
March 2010