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Intel MFSYS35 | Technical Product Specification - Page 1
Intel® Compute Module MFS5000SI Technical Product Specification Intel order number: E15154-007 Revision 1.4 June 2009 Enterprise Platforms and Services Division
Intel MFSYS35 | Technical Product Specification - Page 2
server baseboards support peripheral components and contain a number of highdensity VLSI and power delivery components that need adequate airflow to cool. Intel's own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system
Intel MFSYS35 | Technical Product Specification - Page 3
2.2.3 Compute Module Mechanical Drawings 5 3. Functional Architecture ...6 3.1 Intel® 5000P Memory Controller Hub (MCH 7 3.1.1 System Bus Interface 7 3.1.2 Processor Support 7 3.1.3 3.2 Memory Subsystem 8 Intel® 6321ESB I/O Controller Hub 16 3.2.1 PCI Subsystem ...16 3.2.2 Serial ATA
Intel MFSYS35 | Technical Product Specification - Page 4
29 6.4 Product Environmental/Ecology Markings 29 Appendix A: Integration and Usage Tips 30 Appendix B: BMC Sensor Tables...31 Appendix C: POST Error Messages and Handling 37 Appendix D: Supported Intel® Modular Server System 40 Glossary ...41 Reference Documents ...44 iv Revision
Intel MFSYS35 | Technical Product Specification - Page 5
Minimum Two-DIMM Memory Configuration 12 Figure 8. Recommended Four-DIMM Configuration 13 Figure 9. Single Branch Mode Sparing DIMM Configuration 14 Figure 10. Recovery Jumper Blocks 26 Figure 11. Intel® Modular Server System MFSYS25 40 Revision 1.4 v Intel order number: E15154-007
Intel MFSYS35 | Technical Product Specification - Page 6
List of Tables Intel® Compute Module MFS5000SI TPS List of Tables Table 1. I2C Addresses for Memory Module SMB 9 Table 2. Maximum 8-DIMM System Memory Configuration - x8 Single Rank 10 Table 3. Maximum 8-DIMM System Memory Configuration - x4 Dual Rank 10 Table 4. PCI Bus Segment Characteristics
Intel MFSYS35 | Technical Product Specification - Page 7
C - Post Error Messages and Handling ƒ Appendix D - Supported Intel® Modular Server System 1.2 Intel® Compute Module Use Disclaimer Intel® Modular Server components require adequate airflow to cool. Intel ensures through its own chassis development and testing that when these components are used
Intel MFSYS35 | Technical Product Specification - Page 8
. 2.1 Intel® Compute Module MFS5000SI Feature Set Feature Processors Memory Chipset On-board Connectors/Headers On-board Video On-board Hard Drive Controller LAN Description 771-pin LGA sockets supporting one or two Dual-Core or Quad-Core Intel® Xeon® processors 5000 sequence, with system bus
Intel MFSYS35 | Technical Product Specification - Page 9
and ID LEDs M USB1 and USB2 Connectors O Intel® 6321ESB I/O Controller Hub Q I/O Mezzanine Card Connector Description B Midplane Signal Connector D SAS Controller F Intel® 5000P Memory Controller Hub (MCH) H Voltage Regulator Heatsink J Power Button L Video Connector N CPU #2 Socket P CMOS Battery
Intel MFSYS35 | Technical Product Specification - Page 10
MFS5000SI TPS 2.2.2 External I/O Connector Locations The following drawing shows the layout of the external I/O components for the Intel® Compute Module MFS5000SI. A USB ports 1 and 2 B Video C I/O ports 1 and 2 D NIC ports 1 and 2 E Hard Drive Activity LED F ID LED G Power button H Power
Intel MFSYS35 | Technical Product Specification - Page 11
Intel® Compute Module MFS5000SI TPS 2.2.3 Compute Module Mechanical Drawings 1BProduct Overview Figure 3. Intel® Compute Module MFS5000SI - Hole and Component Positions Revision 1.4 5 Intel order number: E15154-007
Intel MFSYS35 | Technical Product Specification - Page 12
Module MFS5000SI is based on the Intel® 5000 Chipset Family. The chipset is designed for systems based on the Dual-Core and Quad-Core Intel® Xeon® processor 5000 sequence with system bus speeds of 667 MHz, 1066 MHz, and 1333 MHz. The chipset is made up of two main components: the Memory Controller
Intel MFSYS35 | Technical Product Specification - Page 13
about MCH functionality can be obtained from the Intel® 5000 Series Chipsets Server Board Family Datasheet and the Intel® 5000P Memory Controller Hub External Design Specification. 3.1.1 System Bus Interface The MCH is configured for symmetric multi-processing across two independent front
Intel MFSYS35 | Technical Product Specification - Page 14
Intel® Compute Module MFS5000SI TPS 3.1.2.2 Common Enabling Kit (CEK) Design Support The compute module complies with Intel's Common Enabling Kit (CEK) processor mounting and heatsink retention solution. The compute module ships with a CEK spring snapped onto the underside of the server
Intel MFSYS35 | Technical Product Specification - Page 15
Test, DIMM Sparing, and Memory Mirroring. For more information regarding these features, see the Intel® 5000 Series Chipsets Server Board Family Datasheet. 1 DIMM Sparing and Memory Mirroring features will be made available post production launch with a BIOS update. Revision 1.4 9 Intel order
Intel MFSYS35 | Technical Product Specification - Page 16
list of supported memory for the Intel® Compute Module MFS5000SI, refer to the Tested Memory List published in the Intel® Server Configurator Tool. 3.1.3.3 DIMM Population Rules and Supported DIMM Configurations DIMM population rules depend on the operating mode of the memory controller, which is
Intel MFSYS35 | Technical Product Specification - Page 17
is supported by the memory controller, mixed DIMMs configurations are not validated or supported with the Intel® Compute Module MFS5000SI. Refer to section 3.1.3.2 for supported and nonsupported DIMM configuration information. 3.1.3.3.1 Minimum Non-Mirrored Mode Configuration The server board
Intel MFSYS35 | Technical Product Specification - Page 18
MFS5000SI TPS Channel B Channel A Channel C Channel D MCH Branch 0 DIMDMIMDAMIM1DAMIM2DBMIM1DBMIM2DCMIM1DCMIM2DM1D2 Branch 1 TP02300 Figure 7. Recommended Minimum Two-DIMM Memory Configuration Note: The server board supports single DIMM mode operation. Intel only validates and supports
Intel MFSYS35 | Technical Product Specification - Page 19
Intel® Compute Module MFS5000SI TPS Channel B Channel A 2BFunctional Architecture Channel C Channel D MCH Branch 0 DIMDMIMDAMIM1DAMIM2DBMIM1DBMIM2DCMIM1DCMIM2DM1D2 Branch 1 TP02301 Figure 8. Recommended Four-DIMM Configuration Functionally, DIMM slots A2 and B2 could also have been populated
Intel MFSYS35 | Technical Product Specification - Page 20
Intel® Compute Module MFS5000SI TPS DIMM_C2 DIMM_C1 DIMM_D2 DIMM_D1 Channel C Channel D Branch 1 Intel® 5000P/5000X Memory Controller Hub Figure 9. Single Branch Mode Sparing DIMM Configuration note below. ƒ Sparing should be enabled in BIOS setup. ƒ BIOS will configure Rank Sparing Mode. ƒ The
Intel MFSYS35 | Technical Product Specification - Page 21
Intel® Compute Module MFS5000SI TPS 2BFunctional Architecture Note: Use of identical memory is recommended with the Intel® Compute Module MFS5000SI. Mixing memory type, size, speed, rank and/or vendors is not validated and is not supported with this product. Refer to section 3.1.3.2 for supported
Intel MFSYS35 | Technical Product Specification - Page 22
configuration registers. Once configured, each appears to the system as a distinct hardware controller. A primary role of the Intel® 6321ESB I/O Controller Hub is to provide the gateway to all PC-compatible I/O devices and features. The server board uses the following Intel® 6321ESB I/O Controller
Intel MFSYS35 | Technical Product Specification - Page 23
PE6 and PE7 are not used in the Intel® Compute Module MFS5000SI design. 3.2.2 Serial ATA Support The Intel® 6321ESB I/O Controller Hub has an integrated Serial ATA (SATA) controller that supports independent DMA operation on six ports and supports data transfer rates of up to 3.0 Gb/s. These
Intel MFSYS35 | Technical Product Specification - Page 24
Intel® Compute Module MFS5000SI TPS 3.2.4 USB 2.0 Support The USB controller functionality integrated into the Intel® 6321ESB I/O Controller Hub provides the server board with the interface for up to eight USB 2.0 ports. Two external connectors are located on the front edge of the server
Intel MFSYS35 | Technical Product Specification - Page 25
Compute Module MFS5000SI TPS 2BFunctional Architecture 3.4 Network Interface Controller (NIC) Network interface support is provided from the built-in Dual GbE MAC features of the Intel® 6321ESB I/O Controller Hub. These interfaces are routed over the midplane board to the Ethernet switch module in
Intel MFSYS35 | Technical Product Specification - Page 26
MFS5000SI TPS Table 6. Serial Header Pin-out Pin Signal Name 1 DCD 2 DSR 3 RX 4 RTS 5 TX 6 CTS 7 DTR 8 RI 9 GND Serial Port Header Pin-out 3.5.1.2 Floppy Disk Controller The server board does not support a floppy disk controller (FDC) interface. However, the system BIOS
Intel MFSYS35 | Technical Product Specification - Page 27
Intel® Compute Module MFS5000SI TPS 3BConnector / Header Locations and Pin-outs 4. Connector / Header Locations and Pin-outs 4.1 Board Connector Information The following section provides detailed information regarding all connectors, headers and jumpers on the server board. Table 7 lists all
Intel MFSYS35 | Technical Product Specification - Page 28
Header Locations and Pin-outs Intel® Compute Module MFS5000SI TPS 4.3 I/O Connector Pin- server board. The currently available I/O mezzanine card for this server is the Intel® Modular Server Accessory AXXGBIOMEZ, a dual gigabit Ethernet card based on the Intel PE5_MCH_TXP_C3 E9 spare Pin Signal
Intel MFSYS35 | Technical Product Specification - Page 29
Intel® Compute Module MFS5000SI TPS 3BConnector / Header Locations and Pin-outs A10 GND B1 Signal Connector The server board connects to the midplane through a 96-pin Airmax* connector (J3A1) (power is J1A1) to connect the various I/O, management, and control signals of the system. Table 11.
Intel MFSYS35 | Technical Product Specification - Page 30
Pin-outs Intel® Compute Module MFS5000SI TPS A6 GND G7 spare G8 GND H1 SAS_P1_RXN H2 SAS_P1_TXP H3 XE_P2_C_RXN H4 XE_P2_C_TXP H5 SAS_P2_RXN H6 SAS_P2_TXP H7 spare H8 spare I6 GND L8 reserved 4.3.4 Serial Port Connector The server board provides one internal 9-pin Serial 'A' port header (J1B1
Intel MFSYS35 | Technical Product Specification - Page 31
Intel® Compute Module MFS5000SI TPS 3BConnector / Header Locations and Pin-outs Table 6 for the pin-out of the serial header. Table of the external USB connectors (J4K1, J4K2) found on the front edge of the server board. Table 13. External USB Connector Pin-out Pin Signal Name 1 USB_OC#_FB_1
Intel MFSYS35 | Technical Product Specification - Page 32
Module MFS5000SI TPS 5. Jumper Block Settings The server board has several 3-pin jumper blocks that can be used to configure, protect, or recover specific features of the server board. Pin 1 on each jumper block is denoted by an "*" or "▼". 5.1 Recovery Jumper Blocks BIOS Bank Select 32 Default
Intel MFSYS35 | Technical Product Specification - Page 33
Intel® Compute Module MFS5000SI TPS 4BJumper Block Settings Table 14. Recovery Jumpers Jumper Name J7A1: BMC Force Update J4A1: Password Clear Pins 1-2 2-3 1-2 2-3 J1F2: CMOS Clear 1-2 2-3 J3A3: BIOS Bank 1-2 Select 2-3 What happens at system reset ... BMC Firmware Force Update Mode - Enabled
Intel MFSYS35 | Technical Product Specification - Page 34
MFS5000SI TPS 4. Move jumper from Default operating position (pins 2-3) to "Enabled" position (pins 1-2) 5. Close the compute module 6. Reconnect AC power and power up the compute module 7. Perform standard BMC firmware update procedure through the Intel® Modular Server Control software 8. Power
Intel MFSYS35 | Technical Product Specification - Page 35
Intel® Compute Module MFS5000SI TPS 5BProduct Regulatory Requirements 6. Product Regulatory Requirements 6.1 Product Regulatory Requirements The Intel® Compute Module MFS5000SI is evaluated as part of the Intel® Modular Server System MFSYS25/MFSYS35, which requires meeting all applicable system
Intel MFSYS35 | Technical Product Specification - Page 36
board, see the Intel® Compute Module MFS5000SI Tested Memory List in the Intel® Server Configurator Tool. ƒ For a list of Intel supported operating systems, add-in cards, and peripherals for this server board, see the Intel® Compute Module MFS5000SI Tested Hardware and Operating System List. ƒ Only
Intel MFSYS35 | Technical Product Specification - Page 37
Intel® Compute Module MFS5000SI TPS Appendix B: Sensor Tables Appendix B: BMC Sensor Tables Table 15 lists the sensor identification numbers and information regarding the sensor type, name, supported events into the System Event Log (SEL outside sources such as the BIOS) such that the LED will
Intel MFSYS35 | Technical Product Specification - Page 38
Appendix B: Sensor Tables Intel® Compute Module MFS5000SI TPS Sensor Rearm The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states. Rearming the sensors can be done manually or automatically. The following abbreviations are
Intel MFSYS35 | Technical Product Specification - Page 39
Intel® Compute Module MFS5000SI TPS Appendix B: Sensor Tables Name BB Vtt # Sensor Type State 22h Event / Reading Type Event Offset Triggers 3: S3 4: S4 Yes A No Fault Fault Yes A No Fault Fault Yes A No Fault Fault Yes A Yes Revision 1.4 33 Intel order number: E15154-007
Intel MFSYS35 | Technical Product Specification - Page 40
Appendix B: Sensor Tables Intel® Compute Module MFS5000SI TPS Name Hot Swap KVM Session SOL Session SMI Timeout Memory Error Critical Int. DIMM 1-8 Temp Yes A No Fault Fault Yes M Yes None Fault Yes A No Fault Fault Yes A No Fault 34 Revision 1.4 Intel order number: E15154-007
Intel MFSYS35 | Technical Product Specification - Page 41
Intel® Compute Module MFS5000SI TPS Appendix B: Sensor Tables Name # Processor 1,2 Thermal Ctrl % all sensors will be set to generate events for both assertions and de-assertions of all supported sensor offsets as listed in Table 15. Analog Sensor Thresholds Table 16 shows the thresholds
Intel MFSYS35 | Technical Product Specification - Page 42
Appendix B: Sensor Tables Intel® Compute Module MFS5000SI TPS Name BB Vtt BB +1.5V AUX BB +1.5V BB +1.8V BB +3. N/A N/A N/A N/A N/A 100ºC Upper Critical 1.5V 1.65V 1.65V 1.94V 3.62V 3.62V 1.65V 5.5V 13.26V 1.02V 105ºC N/A N/A N/A N/A N/A 50% 36 Revision 1.4 Intel order number: E15154-007
Intel MFSYS35 | Technical Product Specification - Page 43
Processor 02 disabled Processor 01 unable to apply BIOS update Processor 02 unable to apply BIOS update Watchdog timer failed on last boot Operating system boot watchdog timer expired on last boot Baseboard management controller failed self-test Major Major Fatal Major Major Fatal Fatal Major
Intel MFSYS35 | Technical Product Specification - Page 44
management controller in update mode Sensor data record empty System event log full Memory Component could not be configured in the selected RAS mode. System supports a maximum of 16 GB of main memory. Additional memory will not be counted. (This error is S5000V specific.) DIMM_A1 failed Self Test
Intel MFSYS35 | Technical Product Specification - Page 45
Intel® Compute Module MFS5000SI TPS Appendix C: POST Error Messages and Handling Error Code 92A3 to "disabled" in the BIOS Setup Main menu page. If the "POST Error Pause" option is set to "disabled", the system boots the operating system without user-intervention. The default value is set to "
Intel MFSYS35 | Technical Product Specification - Page 46
Appendix D: Supported Intel® Server Chassis Intel® Compute Module MFS5000SI TPS Appendix D: Supported Intel® Modular Server System The Intel® Compute Module MFS5000SI is supported in the following chassis: ƒ Intel® Modular Server System MFSYS25 ƒ Intel® Modular Server System MFSYS35 This section
Intel MFSYS35 | Technical Product Specification - Page 47
Intel® Compute Module MFS5000SI TPS Glossary Configuration and Power Interface Application Processor Advanced Programmable Interrupt Control Application Specific Integrated Circuit Advanced Server Management Interface Basic Input/Output System Built-In Self Test Baseboard Management Controller
Intel MFSYS35 | Technical Product Specification - Page 48
the firmware for the platform hardware) Programmable Logic Device Platform Management Interrupt Power-On Self Test Power Supply Management Interface Pulse-Width Modulation Random Access Memory Reliability, Availability, Serviceability, Usability, and Manageability Reduced Instruction Set
Intel MFSYS35 | Technical Product Specification - Page 49
Intel® Compute Module MFS5000SI TPS Term SIO SMBus SMI SMM SMS SNMP TBD TIM UART UDP UHCI UTC VID VRD Word ZIF Server Input/Output Definition System Management Bus Server Management Interrupt (SMI is the highest priority non-maskable interrupt) Server Management Mode Server Management
Intel MFSYS35 | Technical Product Specification - Page 50
for additional information: ƒ Intel® 5000 Series Chipsets Server Board Family Datasheet ƒ Intel® 5000P Memory Controller Hub External Design Specification ƒ Intel® Enterprise South Bridge 2 (ESB2) External Design Specification ƒ Intel® Modular Server System MFSYS25/MFSYS35 Technical Product

Section	Page
1. Introduction	7
1.1 Chapter Outline	7
1.2 Intel® Compute Module Use Disclaimer	7
2. Product Overview	8
2.1 Intel® Compute Module MFS5000SI Feature Set	8
2.2 Compute Module Layout	9
2.2.1 Connector and Component Locations	9
2.2.2 External I/O Connector Locations	10
2.2.3 Compute Module Mechanical Drawings	11
3. Functional Architecture	12
3.1 Intel® 5000P Memory Controller Hub (MCH)	13
3.1.1 System Bus Interface	13
3.1.2 Processor Support	13
3.1.2.1 Processor Population Rules	13
3.1.2.2 Common Enabling Kit (CEK) Design Support	14
3.1.3 Memory Subsystem	14
3.1.3.1 Memory RASUM Features	15
3.1.3.2 Supported and Nonsupported Memory Configurations	16
3.1.3.3 DIMM Population Rules and Supported DIMM Configurations	16
3.1.3.3.1 Minimum Non-Mirrored Mode Configuration	17
3.1.3.4 Non-mirrored Mode Memory Upgrades	18
3.1.3.4.1 Mirrored Mode Memory Configuration	19
3.1.3.4.2 DIMM Sparing Mode Memory Configuration	19
3.1.3.4.2.1 Single Branch Mode Sparing	20
3.1.3.4.2.2 Dual Branch Mode Sparing	20
3.2 Intel® 6321ESB I/O Controller Hub	22
3.2.1 PCI Subsystem	22
3.2.1.1 PCI32: 32-bit, 33-MHz PCI Bus Segment	23
3.2.1.2 PXA: 64-bit, 133MHz PCI-X Bus Segment	23
3.2.1.3 PE1: One x4 PCI Express* Bus Segment	23
3.2.1.4 PE2: One x4 PCI Express* Bus Segment	23
3.2.1.5 PE4, PE5: Two x4 PCI Express* Bus Segments	23
3.2.1.6 PE6, PE7: Two x4 PCI Express* Bus Segments	23
3.2.2 Serial ATA Support	23
3.2.3 Parallel ATA (PATA) Support	23
3.2.4 USB 2.0 Support	24
3.3 Video Support	24
3.3.1.1 Video Modes	24
3.3.1.2 Video Memory Interface	24
3.4 Network Interface Controller (NIC)	25
3.4.1 Intel® I/O Acceleration Technology	25
3.4.2 MAC Address Definition	25
3.5 Super I/O	25
3.5.1.1 Serial Ports	25
3.5.1.2 Floppy Disk Controller	26
3.5.1.3 Keyboard and Mouse Support	26
3.5.1.4 Wake-up Control	26
4. Connector / Header Locations and Pin-outs	27
4.1 Board Connector Information	27
4.2 Power Connectors	27
4.3 I/O Connector Pin-out Definition	28
4.3.1 VGA Connector	28
4.3.2 I/O Mezzanine Card Connector	28
4.3.3 Midplane Signal Connector	29
4.3.4 Serial Port Connector	30
4.3.5 USB 2.0 Connectors	31
5. Jumper Block Settings	32
5.1 Recovery Jumper Blocks	32
5.1.1 CMOS Clear and Password Reset Usage Procedure	33
5.1.2 BMC Force Update Procedure	33
5.1.3 System Status LED – BMC Initialization	34
6. Product Regulatory Requirements	35
6.1 Product Regulatory Requirements	35
6.2 Product Regulatory Compliance and Safety Markings	35
6.3 Product Environmental/Ecology Requirements	35

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Intel

Compute Module MFS5000SI

Technical Product Specification

Intel order number: E15154-007

Revision 1.4

June 2009

Enterprise Platforms and Services Division