Intel SL6NQ Specification Update

Intel SL6NQ - Xeon 2.4 GHz/533MHz/512 KB CPU Processor 2.4GHz Manual

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  • Intel SL6NQ | Specification Update - Page 1
    Specification Update January 2007 Notice: The Intel® Xeon® processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in
  • Intel SL6NQ | Specification Update - Page 2
    features or instructions marked "reserved" or "undefined." Intel reserves Intel's website at http://developer.intel.com/design/litcentr. Intel®, the Intel® logo, Pentium®, Pentium® III Xeon™, Celeron, Intel® NetBurst™ and Intel® Xeon™ are trademarks or registered trademarks of Intel® Corporation
  • Intel SL6NQ | Specification Update - Page 3
    Contents Revision History ...5 Preface ...9 Identification Information 10 Mixed Steppings in DP Systems 18 Summary Table of Changes 20 Errata...27 Specification Changes...51 Specification Clarifications 53 Documentation Changes 56 Intel® Xeon® Processor Specification Update 3
  • Intel SL6NQ | Specification Update - Page 4
    4 Intel® Xeon® Processor Specification Update
  • Intel SL6NQ | Specification Update - Page 5
    and RSQRTSS instruction specification clarification. processor with Processor Signature=0F24h B0 Step. • Added new S-spec processors to Processor processor. • Corrected 3 mislabeled S-Spec Table parts. • Added erratum P45 to Processor S-specs SL687 and SL65T to Processor ID table. • Updated datasheet
  • Intel SL6NQ | Specification Update - Page 6
    (Intel® Xeon® Processor with 533 MHz Front Side Bus. • Added new processor with Processor Signature=0F27h C1 Step. • Added New S-specs to the processor ID table. • All References to CPUID are now renamed Processor Signature. • Added reference to IA-32 Intel® Architecture Software Developer's Manual
  • Intel SL6NQ | Specification Update - Page 7
    2003 • Added erratum P64. • Updated erratum P9, P22, P39. • Added new Processor - Intel® Xeon® Processor with 1-MB L3 Cache at 3.20 GHz with Processor Signature=0F25H (M0 Stepping). • Added New S-specs - Intel® Xeon® Processor with 1-MB L3 Cache at 3.20 GHz. September 2003 October 2003 • Added
  • Intel SL6NQ | Specification Update - Page 8
    Changes. • Updated the Software Developer Manual Name. October 2006 • Made changes to the DP Platform Population Matrix. November 2006 -056 • Updated Summary Table of Changes. December 2006 -057 • Updated Summary Table of Changes. January 2007 8 Intel® Xeon® Processor Specification Update
  • Intel SL6NQ | Specification Update - Page 9
    with 533 MHz Front Side Bus at 2 GHz to 3.20 GHz Datasheet 252135 Low Voltage Intel® Xeon® Processor at 1.60 GHz, 2.0 GHz, and 2.4 GHz Datasheet 273766 Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual, Volumes 1, 2A, 2B, 3A, and 3B 253665, 253666, 253667, 253668 and 253669
  • Intel SL6NQ | Specification Update - Page 10
    Markings, 256-KB Cache (603-pin Interposer INT-mPGA Package) Figure 1. Top Side Processor Marking Intel® Xeon™ i(m) ©'01 Figure 2. Bottom Side Processor Marking 2D Matrix OR Dynamic Laser Mark Area D0096109 0032 ATPO Mark (8 Characters) Serial Number Mark (4 digits) Dynamic Laser Mark Area
  • Intel SL6NQ | Specification Update - Page 11
    Interposer INT-mPGA Package and 604-pin Fc-mPGA2 Package) Figure 3. Top Side Processor Marking Intel® Xeon™ i m c '02 2D Matrix Includes ATPO and Serial Number (front end mark) Figure 4. Bottom Side Processor Marking Dynamic Laser Mark Area Speed / Cache / Bus / Voltage S-Spec Country of Assy
  • Intel SL6NQ | Specification Update - Page 12
    , and the model field of the Device ID register accessible through Boundary Scan. 3. The Brand ID corresponds to bits [7:0] of the EBX register after the Processor Signature instruction is executed with a 1 in the EAX register. 12 Intel® Xeon® Processor Specification Update
  • Intel SL6NQ | Specification Update - Page 13
    on the Processor Signature instruction. Table 1. Intel® Xeon® Processor Identification and Package Information (Sheet 1 of 5) S-Spec Number SL4WX SL56G SL4WY SL4ZT SL56N SL56H SL5TD SL5U6 SL5TE SL5U7 SL5TH SL5U8 SL5Z8 SL622 SL5Z9 SL623 Core Stepping C1 Processor Signature 0F0Ah Speed Core/Front
  • Intel SL6NQ | Specification Update - Page 14
    Information Table 1. Intel® Xeon® Processor Identification and Package Information (Sheet 2 of 5) S-Spec Number SL5ZA SL624 SL687 SL65T SL6EL SL6JX SL6EM SL6JY SL6EN SL6JZ SL6EP SL6K2 SL6EQ SL6K3 SL6M7 SL6MS SL6NP SL6NQ Core Stepping B0 Processor Signature Speed Core/Front Side Bus
  • Intel SL6NQ | Specification Update - Page 15
    Intel® Xeon® Processor Identification and Package Information (Sheet 3 of 5) S-Spec Number SL6NR SL6NS SL6RQ SL6GD SL6GF SL6GG SL6GH SL6RR SL6GV SL6GV SL6W3 SL6YS SL6W6 SL6YT SL6W7 SL6YU SL6W8 SL6YV SL6W9 SL6YW SL6WA SL6YX SL6WB SL6YY SL6XK SL6XL Core Stepping C1 Processor Signature Speed Core
  • Intel SL6NQ | Specification Update - Page 16
    1. Intel® Xeon® Processor Identification and Package Information (Sheet 4 of 5) S-Spec Number SL74T SL6VK SL6YM SL6VL SL6YN SL6VM SL6NR SL6VN SL6YQ SL6VP SL6YR SL73K SL72C SL73L SL72D SL73M SL72E SL73N SL72F SL73P SL72G SL73Q SL72Y SL7AE SL7BW SL7D5 SL7DG SL7D4 SL7DF SL8TJ SL8TK Core Stepping
  • Intel SL6NQ | Specification Update - Page 17
    . 4. These parts require the inputs from A20M#, IGNNE#, LINT[1]/NMI and LINT[0]/INTR pins during RESET to set the correct core to bus frequency ratio. 5. These parts are the Intel® Xeon® Processor with 533 MHz Front Side Bus. 6. These parts have a VID of 1.525V. 7. These parts are the Low Voltage
  • Intel SL6NQ | Specification Update - Page 18
    Systems Mixed Steppings in DP Systems Intel Corporation fully supports mixed steppings of Intel Xeon processors. The following list and processor matrix describes the requirements to support mixed steppings: • Mixed steppings are only supported with processors that have identical family numbers as
  • Intel SL6NQ | Specification Update - Page 19
    is able to support. See the Table 1 for details on which processors are affected by these errata. 2. This Matrix also applies to the Intel® Xeon® Processor with 533 MHz Front Side Bus, Low Voltage Intel® Xeon® Processor, Intel® Xeon® Processor with 1-MB L3 cache, and Intel® Xeon® Processor with 2-MB
  • Intel SL6NQ | Specification Update - Page 20
    Intel® Xeon® processor MP with 1MB L2 cache K = Mobile Intel® Pentium® III processor L = Intel® Celeron® D processor M = Mobile Intel® Celeron® processor N = Intel ® Pentium® 4 processor O = Intel® Xeon® processor MP P = Intel® Xeon® processor Q = Mobile Intel® Pentium® 4 processor supporting Hyper
  • Intel SL6NQ | Specification Update - Page 21
    and Intel® Pentium® D processor on 65 nm process AB = Intel® Pentium® 4 processor on 65 nm process AC = Intel® Celeron® Processor in 478 Pin Package AG= Dual-Core Intel® Xeon® Processor 5100 Series AH= Intel® Core™2 Duo mobile Processor AI= Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo
  • Intel SL6NQ | Specification Update - Page 22
    X X Fixed Performance counter may contain incorrect value after being stopped P8 X Fixed REP MOV instruction with overlapping source and destination may result in data corruption P9 X X X X X X may not complete with an IOQ depth of one 22 Intel® Xeon® Processor Specification Update
  • Intel SL6NQ | Specification Update - Page 23
    pushed on to stack after execution of an LSS instruction P37 X X Fixed Buffer on resistance may exceed specification P38 X Fixed Instruction pointer stored on stack may become invalid P39 X cache may contain stale data in the exclusive state Intel® Xeon® Processor Specification Update 23
  • Intel SL6NQ | Specification Update - Page 24
    #GP exception handler P66 X X X X X X X No Fix Locks and SMC detection may cause the processor to temporarily hang P67 X X X X X X X No Fix Incorrect debug exception (#DB) may occur when a data breakpoint is set on a FP instruction 24 Intel® Xeon® Processor Specification Update
  • Intel SL6NQ | Specification Update - Page 25
    instruction with Fast Strings enabled P82 X X X X X X X No Fix Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt P83 X X X X X X X No Fix The Processor May Report a #TS Instead of a #GP Fault Intel® Xeon® Processor Specification
  • Intel SL6NQ | Specification Update - Page 26
    SPECIFICATION CHANGES P1 Context ID feature added to processor signature instruction feature Flags/IA32_MISC_Enable registers Specification Clarifications No. SPECIFICATION DOCUMENTATION CHANGES None for this revision of the Specification Update. 26 Intel® Xeon® Processor Specification Update
  • Intel SL6NQ | Specification Update - Page 27
    byte Problem: Some invalid opcodes require a ModRM byte and other following bytes, while others do not. The invalid opcode 0FFFh did not require a ModRM in previous generation microprocessors such as Pentium II or Pentium III processors, but it is required in the Intel Xeon processor Implication
  • Intel SL6NQ | Specification Update - Page 28
    value Problem: instruction with overlapping source and destination may result in data corruption When fast strings are enabled and a REP MOV instruction is used to move a string and the source and destination strings overlap by 56 bytes or less, data corruption may occur. 28 Intel® Xeon® Processor
  • Intel SL6NQ | Specification Update - Page 29
    from its corresponding store unlock Problem: A use-once protocol is employed to ensure that the processor in a multi-agent system Since use-once does not apply to stores, the store unlock instructions go out as WB memory type. The full sequence on the Intel® Xeon® Processor Specification Update 29
  • Intel SL6NQ | Specification Update - Page 30
    will remain pending. However, while attempting to execute the first instruction of the MCE handler, the SMI# will be recognized and the processor will attempt to execute the SMM handler. If the SMM handler not be set. In instances where an L1 parity error Intel® Xeon® Processor Specification Update
  • Intel SL6NQ | Specification Update - Page 31
    serialized instructions before the UC load will reduce the occurrence of this erratum. Implication: Certain debug mechanisms do not function as expected on the processor. Workaround: None at this time. Status: For the steppings affected, see the Summary Table of Changes. Intel® Xeon® Processor
  • Intel SL6NQ | Specification Update - Page 32
    Table of Changes. P16 Problem: EMON event counting of x87 loads may not work as expected If a performance counter is set to count x87 loads and floating-point (FP) exceptions are unmasked, the FPU Operand (Data) Pointer (FDP) may become corrupted. 32 Intel® Xeon® Processor Specification Update
  • Intel SL6NQ | Specification Update - Page 33
    . P20 Problem: Speculative page-fault may cause livelock If the processor detects a page-fault, which is corrected before the operating system page-fault handler can be called (e.g., a second processor or DMA activity modifies the page tables and the Intel® Xeon® Processor Specification Update
  • Intel SL6NQ | Specification Update - Page 34
    SQRTSD instructions when DAZ mode is enabled. Software could enable FTZ mode to ensure that negative denormals are not generated by computation prior to execution of the SQRTPD or SQRTSD instructions. Status: For the steppings affected, see the Summary Table of Changes. 34 Intel® Xeon® Processor
  • Intel SL6NQ | Specification Update - Page 35
    P25 Multiprocessor boot protocol may not complete with an IOQ depth of one Problem: When the in-order queue (IOQ) depth is managed by the chipset the faulting instruction. Status: For the steppings affected, see the Summary Table of Changes. Intel® Xeon® Processor Specification Update 35
  • Intel SL6NQ | Specification Update - Page 36
    . P28 FSW may not be completely restored after page-fault on FRSTOR or FLDENV instructions Problem: If the FPU operating environment or FPU state (operating environment and register stack) steppings affected, see the Summary Table of Changes 36 Intel® Xeon® Processor Specification Update
  • Intel SL6NQ | Specification Update - Page 37
    Problem: processor should recycle the RFO until the ECC error is handled. Due to this erratum, the processor does not recycle the RFO and attempt to service support precise-event-based sampling (PEBS). A number of performance metrics that support Intel® Xeon® Processor Specification Update 37
  • Intel SL6NQ | Specification Update - Page 38
    Intel® Xeon® Processor and Intel® 860 Chipset Platform Design Guide are not expected to be affected. Workaround: No workaround is necessary for systems with margin sufficient to accept a higher RON. Status: For the steppings affected, see the Summary Table of Changes. P38 Problem: Instruction
  • Intel SL6NQ | Specification Update - Page 39
    to GP fault handler on the first logical processor. Implication: The instruction pointer stored on the stack may be invalid, Summary Table of Changes. P41 Problem: Global bit incorrectly set for secondary logical processors in ITLB Due to a boundary Intel® Xeon® Processor Specification Update 39
  • Intel SL6NQ | Specification Update - Page 40
    DP platforms Problem: A system bus address parity error may be signaled if two processors run at odd core frequency to system Bus-ratios (17:1, 19:1, etc.) on DP processor platforms. This in the Invalid (I) state and the following scenario occurs: 40 Intel® Xeon® Processor Specification Update
  • Intel SL6NQ | Specification Update - Page 41
    the Summary Table of Changes. P48 Erroneous BIST result found in EAX register after reset Problem: The processor may show an erroneous built-in self test (BIST) result in the EAX register the steppings affected, see the Summary Table of Changes. Intel® Xeon® Processor Specification Update 41
  • Intel SL6NQ | Specification Update - Page 42
    shutdown Problem: When the Processor Signature instruction is executed with EAX = 2 on a processor instructions are executed. No commercial operating system is known to be impacted by this erratum. Status: For the steppings affected, see the Summary Table of Changes. 42 Intel® Xeon® Processor
  • Intel SL6NQ | Specification Update - Page 43
    (RF) bit in the EFLAGS register. Implication: The processor will break at the instruction breakpoint address instead of single stepping. Workaround: Execution after the break will continue if DR7 bit 1 (Global Breakpoint Enable) is manually cleared. Status: For the steppings affected, see the
  • Intel SL6NQ | Specification Update - Page 44
    making forward progress, since the logical processor will not be able to service any pending event. This erratum Problem: Implication: The state of the resume flag (RF flag) in a task-state segment (TSS) may be incorrect After executing a JMP instruction Intel® Xeon® Processor Specification Update
  • Intel SL6NQ | Specification Update - Page 45
    of Changes. P63 Changes to CR3 register do not fence pending instruction page Problem: When software writes to the CR3 register, it is expected branch instruction. Workaround: None at this time. Status: For the steppings effected, see the Summary Table of Changes. Intel® Xeon® Processor
  • Intel SL6NQ | Specification Update - Page 46
    hang Problem: The processor may temporarily hang in an HT Technology enabled system if one logical processor executes a synchronization loop that includes one or more bus locks and is waiting for release by the other logical processor. If the releasing logical processor is executing instructions
  • Intel SL6NQ | Specification Update - Page 47
    processor supporting Hyper-Threading Technology Problem: When a processor supporting HT Technology enables On-Demand Clock modulation on both logical processors, the processor Intel® Architecture Software Developer's Manual incorrect instruction stream Intel® Xeon® Processor Specification Update 47
  • Intel SL6NQ | Specification Update - Page 48
    . Software that conforms to the IA-32 Intel® Architecture Software Developer's Manual will operate correctly. If the guidelines in the IA-32 Intel® Architecture Software Developer's Manual are not followed, stale data may be loaded into the processor's translation lookaside buffer (TLB) and used for
  • Intel SL6NQ | Specification Update - Page 49
    transactions to that cache line, the central agent's invalidating snoop will get a clean snoop result. Or 2. Snoop filtering central agents can: a. Not use processor-originated BWIL or BLW transactions to update their snoop filter information, or Intel® Xeon® Processor Specification Update 49
  • Intel SL6NQ | Specification Update - Page 50
    access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. 50 Intel® Xeon® Processor Specification Update
  • Intel SL6NQ | Specification Update - Page 51
    's Manual, Volumes 1, 2A, 2B, 3A, and 3B (Order Numbers 253665, 253666, 253667, and 253668, respectively) All Specification Changes will be incorporated into a future version of the appropriate Intel® Xeon® processor documentation. P1 Context ID feature added to processor signature instruction
  • Intel SL6NQ | Specification Update - Page 52
    ID. A value of '1' indicates the L1 data cache mode can be set to either adaptive mode or shared mode. A value of '0' this feature is not supported. See definition of the IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) for more details. 52 Intel® Xeon® Processor Specification Update
  • Intel SL6NQ | Specification Update - Page 53
    , Volume 3: System Programming Guide, the Time-Stamp Counter definition has been updated to include support for the future processors. This change will be incorporated in the next revision of the IA-32 Intel® Architecture Software Developer's Manual. Intel® Xeon® Processor Specification Update 53
  • Intel SL6NQ | Specification Update - Page 54
    supports the use of the TSC as a wall clock timer even if the processor core changes frequency. This is the architectural behavior moving forward. Note: To determine average processor clock frequency, Intel for Pentium 4, Intel Xeon, P6 family, and Pentium processors. Normally, the RDTSC instruction
  • Intel SL6NQ | Specification Update - Page 55
    Specification Clarifications The RDMSR and WRMSR instructions read and write the time-stamp counter, treating the time-stamp counter as an ordinary MSR (address 10H). In the Pentium 4, Intel Xeon, and P6 family processors, all 64-bits of the time-stamp counter are read using RDMSR (just as with
  • Intel SL6NQ | Specification Update - Page 56
    Side Bus at 2 GHz to 3.20 GHz Datasheet (Order Number 252135) • Low Voltage Intel® Xeon® Processor at 1.60 GHz to 2.4 GHz Datasheet (Order Number 273766) • Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual, Volumes 1, 2A, 2B, 3A, and 3B (Order Numbers 253665, 253666, 253667, and
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Intel
®
Xeon
®
Processor
Specification Update
January 2007
Document Number: 249678-05
7
Notice:
The Intel
®
Xeon
®
processor may contain design defects or errors known as errata which
may cause the product to deviate from published specifications. Current characterized errata are
documented in this specification update.