ASRock B660 Pro RS User Manual - Page 68

DRAM Timing Configuration, GT Unlimited Current Limit

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B660 Pro RS save power, while a higher limit may improve performance. GT Unlimited Current Limit To unlock voltage regulator current limit completely, you can set this option to Enabled. GT Current Limit Configure the current limit of the GT slice. A lower limit can protect the CPU and save power, while a higher limit may improve performance. DRAM Configuration Memory Information Allows users to browse the serial presence detect (SPD) and Intel extreme memory profile (XMP) for DDR4 modules. DRAM Timing Configuration Load XMP Setting Load XMP settings to overclock the memory and perform beyond standard specifications. DRAM Reference Clock Select Auto for optimized settings. DRAM Frequency If [Auto] is selected, the motherboard will detect the memory module(s) inserted and assign the appropriate frequency automatically. DRAM Gear Mode High gear is good for high frequency. Primary Timing CAS# Latency (tCL) The time between sending a column address to the memory and the beginning of the data in response. RAS# to CAS# Delay and Row Precharge (tRCDtRP) RAS# to CAS# Delay : The number of clock cycles required between the opening of a row of memory and accessing columns within it. 61 English

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61
English
B660 Pro RS
save power, while a higher limit may improve performance.
GT Unlimited Current Limit
To unlock voltage regulator current limit completely, you can set this option to
Enabled.
GT Current Limit
Configure the current limit of the GT slice. A lower limit can protect the CPU and
save power, while a higher limit may improve performance.
DRAM Configuration
Memory Information
Allows users to browse the serial presence detect (SPD) and Intel extreme memory profile
(XMP) for DDR4 modules.
DRAM Timing Configuration
Load XMP Setting
Load XMP settings to overclock the memory and perform beyond standard
specifications.
DRAM Reference Clock
Select Auto for optimized settings.
DRAM Frequency
If [Auto] is selected, the motherboard will detect the memory module(s) inserted
and assign the appropriate frequency automatically.
DRAM Gear Mode
High gear is good for high frequency.
Primary Timing
CAS# Latency (tCL)
°e time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay and Row Precharge (tRCDtRP)
RAS# to CAS# Delay : °e number of clock cycles required between the opening of a row
of memory and accessing columns within it.