ASRock B760M Pro RS Software/BIOS Setup Guide - Page 55

P-Core PLL Voltage Offset

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Intel Z790/H770/B760 Series VDDQ Voltage Allows you to configure the VDDQ Voltage supported by PMIC at DRAM side. The VDDQ output can be measured through PMIC ADC with step size 0.015V. VDDQ information is contained in memory SPD and XMP. You can check it via the Memory Information tool. Configuration options: [JEDEC Standard] [OC Demand] VDDQ Voltage Range JEDEC Standard ranges from 0.800V to 1.435V. OC Demand ranges from 0.800V to 2.070V. OC Demand may not be applied if PMIC OC CAP is JEDEC PMIC. You can check it via the Memory Information tool. Configuration options: [JEDEC Standard] [OC Demand] VPP Voltage Allows you to configure the VPP Voltage supported by PMIC at DRAM side. The VPP output can be measured through PMIC ADC with step size 0.015V. VPP information is contained in memory SPD and XMP. You can check it via the Memory Information tool. VDD Eventual Voltage Allows you to configure the final VDD Voltage. VDDQ Eventual Voltage Allows you to configure the final VDDQ Voltage. VPP Eventual Voltage Allows you to configure the final VPP Voltage. PMIC Protection Unlock Allows you to configure PMIC Protection Unlock settings. Configuration options: [Auto] [Enabled] PLL Voltage Configuration P-Core PLL Voltage Offset PLL Voltage Offset value ranges from 0 to 15 bins, and each bin is 15mV. Adding 5 or more bins will help to increase the range of this domain frequency in extreme overclocking conditions. The best bins will be different on each processor. You have to find the best bins for your own processor. E-Core PLL Voltage Offset PLL Voltage Offset value ranges from 0 to 15 bins, and each bin is 15mV. Adding 5 or more 51

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Intel Z790/H770/B760 Series
VDDQ Voltage
Allows you to configure the VDDQ Voltage supported by PMIC at DRAM side. °e VDDQ
output can be measured through PMIC ADC with step size 0.015V. VDDQ information is
contained in memory SPD and XMP. You can check it via the Memory Information tool.
Configuration options: [JEDEC Standard] [OC Demand]
VDDQ Voltage Range
JEDEC Standard ranges from 0.800V to 1.435V. OC Demand ranges from 0.800V to 2.070V.
OC Demand may not be applied if PMIC OC CAP is JEDEC PMIC. You can check it via
the Memory Information tool.
Configuration options: [JEDEC Standard] [OC Demand]
VPP Voltage
Allows you to configure the VPP Voltage supported by PMIC at DRAM side. °e VPP
output can be measured through PMIC ADC with step size 0.015V. VPP information is
contained in memory SPD and XMP. You can check it via the Memory Information tool.
VDD Eventual Voltage
Allows you to configure the final VDD Voltage.
VDDQ Eventual Voltage
Allows you to configure the final VDDQ Voltage.
VPP Eventual Voltage
Allows you to configure the final VPP Voltage.
PMIC Protection Unlock
Allows you to configure PMIC Protection Unlock settings.
Configuration options: [Auto] [Enabled]
PLL Voltage Configuration
P-Core PLL Voltage Offset
PLL Voltage Offset value ranges from 0 to 15 bins, and each bin is 15mV. Adding 5 or more
bins will help to increase the range of this domain frequency in extreme overclocking
conditions. °e best bins will be different on each processor. You have to find the best bins
for your own processor.
E-Core PLL Voltage Offset
PLL Voltage Offset value ranges from 0 to 15 bins, and each bin is 15mV. Adding 5 or more