ASRock Fatal1ty Z170 Gaming-ITX/ac User Manual - Page 63
tWRWR_sg, tWRWR_dg, tWRWR_dr, tWRWR_dd, RTL CH A, RTL CH B, IO-L CH A, IO-L CH B, Fourth Timing,
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tWRWR_sg Conigure between module write to write delay. tWRWR_dg Conigure between module write to write delay. tWRWR_dr Conigure between module write to write delay. tWRWR_dd Conigure between module write to write delay. RTL (CH A) Conigure round trip latency for channel A. RTL (CH B) Conigure round trip latency for channel B. IO-L (CH A) Conigure IO latency for channel A. IO-L (CH B) Conigure IO latency for channel B. Fourth Timing twRPRE Conigure twRPRE. Write_Early_ODT Conigure Write_Early_ODT. tAONPD Conigure tAONPD. tXP Conigure tXP. tXPDLL Conigure tXPDLL. 56 English
56
English
tWRWR_sg
Con±gure between module write to write delay.
tWRWR_dg
Con±gure between module write to write delay.
tWRWR_dr
Con±gure between module write to write delay.
tWRWR_dd
Con±gure between module write to write delay.
RTL (CH A)
Con±gure round trip latency for channel A.
RTL (CH B)
Con±gure round trip latency for channel B.
IO-L (CH A)
Con±gure IO latency for channel A.
IO-L (CH B)
Con±gure IO latency for channel B.
Fourth Timing
twRPRE
Con±gure twRPRE.
Write_Early_ODT
Con±gure Write_Early_ODT.
tAONPD
Con±gure tAONPD.
tXP
Con±gure tXP.
tXPDLL
Con±gure tXPDLL.