ASRock H610M-ITX/ac User Manual - Page 56

DRAM Timing Configuration, DRAM Reference Clock

Page 56 highlights

GT Current Limit Configure the current limit of the GT slice. A lower limit can protect the CPU and save power, while a higher limit may improve performance. PSU Select Guide Adjust CPU Power Limit and ICCMAX settings to avoid system reboot when using low wattage power supplies. DRAM Configuration Memory Information Allows users to browse the serial presence detect (SPD) and Intel extreme memory profile (XMP) for DDR4 modules. DRAM Timing Configuration DRAM Reference Clock Select Auto for optimized settings. DRAM Frequency If [Auto] is selected, the motherboard will detect the memory module(s) inserted and assign the appropriate frequency automatically. DRAM Gear Mode High gear is good for high frequency. Primary Timing CAS# Latency (tCL) The time between sending a column address to the memory and the beginning of the data in response. RAS# to CAS# Delay (tRCD) RAS# to CAS# Delay : The number of clock cycles required between the opening of a row of memory and accessing columns within it. Row Precharge (tRP) Row Precharge: The number of clock cycles required between the issuing of the precharge command and opening the next row. 48 English

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48
English
GT Current Limit
Configure the current limit of the GT slice. A lower limit can protect the CPU and
save power, while a higher limit may improve performance.
PSU Select Guide
Adjust CPU Power Limit and ICCMAX settings to avoid system reboot when using
low wattage power supplies.
DRAM Configuration
Memory Information
Allows users to browse the serial presence detect (SPD) and Intel extreme memory profile
(XMP) for DDR4 modules.
DRAM Timing Configuration
DRAM Reference Clock
Select Auto for optimized settings.
DRAM Frequency
If [Auto] is selected, the motherboard will detect the memory module(s) inserted
and assign the appropriate frequency automatically.
DRAM Gear Mode
High gear is good for high frequency.
Primary Timing
CAS# Latency (tCL)
°e time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay (tRCD)
RAS# to CAS# Delay : °e number of clock cycles required between the opening of a row
of memory and accessing columns within it.
Row Precharge (tRP)
Row Precharge: °e number of clock cycles required between the issuing of the precharge
command and opening the next row.