ASRock QC5000M User Manual - Page 33

DRAM Timing Control, Power Down Enable, Bank Interleaving, CAS# Latency tCL, Row Precharge Time tRP

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DRAM Timing Control Power Down Enable Use this item to enable or disable DDR power down mode. Bank Interleaving Interleaving allows memory accesses to be spread out over banks on the same node, or accross nodes, decreasing access contention. CAS# Latency (tCL) he time between sending a column address to the memory and the beginning of the data in response. RAS# to CAS# Delay (tRCD) he number of clock cycles required between the opening of a row of memory and accessing columns within it. Row Precharge Time (tRP) he number of clock cycles required between the issuing of the precharge command and opening the next row. RAS# Active Time (tRAS) he number of clock cycles required between a bank active command and issuing the precharge command. 28 English

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English
28
DRAM Timing Control
Power Down Enable
Use this item to enable or disable DDR power down mode.
Bank Interleaving
Interleaving allows memory accesses to be spread out over banks on the same node, or
accross nodes, decreasing access contention.
CAS# Latency (tCL)
He time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay (tRCD)
He number of clock cycles required between the opening of a row of memory and
accessing columns within it.
Row Precharge Time (tRP)
He number of clock cycles required between the issuing of the precharge command
and opening the next row.
RAS# Active Time (tRAS)
He number of clock cycles required between a bank active command and issuing the
precharge command.