ASRock QC6000M User Manual - Page 32

RAS# Active Time tRAS

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QC7000M / QC6000M DRAM Timing Control Power Down Enable Use this item to enable or disable DDR power down mode. Bank Interleaving Interleaving allows memory accesses to be spread out over banks on the same node, or accross nodes, decreasing access contention. CAS# Latency (tCL) The time between sending a column address to the memory and the beginning of the data in response. RAS# to CAS# Delay (tRCD) The number of clock cycles required between the opening of a row of memory and accessing columns within it. Row Precharge Time (tRP) The number of clock cycles required between the issuing of the precharge command and opening the next row. RAS# Active Time (tRAS) The number of clock cycles required between a bank active command and issuing the precharge command. Command Rate (CR) The delay between when a memory chip is selected and when the first active command can be issued. RAS# Cycle Time (tRC) Use this item to change RAS# Cycle Time (tRC) Auto/Manual setting. Write Recovery Time (tWR) The amount of delay that must elapse after the completion of a valid write operation, before an active bank can be precharged. Refresh Cycle Time (tRFC) The number of clocks from a Refresh command until the first Activate command to the same rank. 27 English

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QC7000M / QC6000M
27
English
DRAM Timing Control
Power Down Enable
Use this item to enable or disable DDR power down mode.
Bank Interleaving
Interleaving allows memory accesses to be spread out over banks on the same node, or
accross nodes, decreasing access contention.
CAS# Latency (tCL)
°e time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay (tRCD)
°e number of clock cycles required between the opening of a row of memory and
accessing columns within it.
Row Precharge Time (tRP)
°e number of clock cycles required between the issuing of the precharge command
and opening the next row.
RAS# Active Time (tRAS)
°e number of clock cycles required between a bank active command and issuing the
precharge command.
Command Rate (CR)
°e delay between when a memory chip is selected and when the first active command can
be issued.
RAS# Cycle Time (tRC)
Use this item to change RAS# Cycle Time (tRC) Auto/Manual setting.
Write Recovery Time (tWR)
°e amount of delay that must elapse aſter the completion of a valid write operation,
before an active bank can be precharged.
Refresh Cycle Time (tRFC)
°e number of clocks from a Refresh command until the first Activate command to
the same rank.