ASRock Z170 Pro4S User Manual - Page 54

Write to Read Delay tWTR_L

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Z170M Pro4S Command Rate (CR) he delay between when a memory chip is selected and when the irst active command can be issued. Secondary Timing Write Recovery Time (tWR) he amount of delay that must elapse ater the completion of a valid write operation, before an active bank can be precharged. Refresh Cycle Time (tRFC) he number of clocks from a Refresh command until the irst Activate command to the same rank. RAS to RAS Delay (tRRD_L) he number of clocks between two rows activated in diferent banks of the same rank. RAS to RAS Delay (tRRD_S) he number of clocks between two rows activated in diferent banks of the same rank. Write to Read Delay (tWTR_L) he number of clocks between the last valid write operation and the next read command to the same internal bank. Write to Read Delay (tWTR_S) he number of clocks between the last valid write operation and the next read command to the same internal bank. Read to Precharge (tRTP) he number of clocks that are inserted between a read command to a row precharge command to the same rank. Four Activate Window (tFAW) he time window in which four activates are allowed the same rank. CAS Write Latency (tCWL) Conigure CAS Write Latency. 49 English

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49
English
Z170M Pro4S
Command Rate (CR)
He delay between when a memory chip is selected and when the ±rst active command can
be issued.
Secondary Timing
Write Recovery Time (tWR)
He amount of delay that must elapse aTer the completion of a valid write operation,
before an active bank can be precharged.
Refresh Cycle Time (tRFC)
He number of clocks from a Refresh command until the ±rst Activate command to
the same rank.
RAS to RAS Delay (tRRD_L)
He number of clocks between two rows activated in diµerent banks of the same
rank.
RAS to RAS Delay (tRRD_S)
He number of clocks between two rows activated in diµerent banks of the same
rank.
Write to Read Delay (tWTR_L)
He number of clocks between the last valid write operation and the next read command to
the same internal bank.
Write to Read Delay (tWTR_S)
He number of clocks between the last valid write operation and the next read command to
the same internal bank.
Read to Precharge (tRTP)
He number of clocks that are inserted between a read command to a row pre-
charge command to the same rank.
Four Activate Window (tFAW)
He time window in which four activates are allowed the same rank.
CAS Write Latency (tCWL)
Con±gure CAS Write Latency.