Acer Aspire 5336 Service Guide - Page 163

Post Codes These tables describe the POST codes and descriptions during the POST. Post Code Range SEC PEI DXE BDS SMM S3 ASL Phase PostBDS Reserved POST Code Range 0x01 - 0x0F 0x70 - 0x9F 0x40 - 0x6F 0x10 - 0x3F 0xA0 - 0xBF 0xC0 - 0xCF 0x51 - 0x55 0xE1 - 0xE4 0xF9 - 0xFE 0xD8 - 0xE0 0xE5 - 0xF8 SEC Phase POST Code Table Functionality Name (Include\ PostCode.h) SEC_SYSTEM_POWER_ON Phase SEC SEC_BEFORE_MICROCODE_PATCH SEC_AFTER_MICROCODE_PATCH SEC_SETUP_CAR_OK SEC_GO_TO_SECSTARTUP SEC_GO_TO_PEICORE SEC SEC SEC SEC SEC Post Code 1 2 3 7 9 0A Description CPU power on and switch to Protected mode Patching CPU microcode Setup Cache as RAM Cache as RAM test Setup BIOS ROM cache Enter Boot Firmware Volume PEI Phase POST Code Table: Functionality Name (Include\ PostCode.h) PEI_SIO_INIT PEI_CPU_REG_INIT PEI_CPU_AP_INIT PEI_CPU_HT_RESET PEI_PCIE_MMIO_INIT PEI_NB_REG_INIT PEI_SB_REG_INIT PEI_PCIE_TRAINING PEI_TPM_INIT PEI_SMBUS_INIT PEI_PROGRAM_CLOCK_GEN PEI_MEMORY_INIT PEI_MEMORY_INIT_FOR_CRISIS PEI_MEMORY_INSTALL PEI_SWITCH_STACK Phase PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI PEI Post Code 70 71 72 73 74 75 76 77 78 79 7A 7E 7F 80 82 Description Super I/O Initialization CPU Early Initialization Multi-processor Early Initial HyperTransport Initialization PCIE MMIO BAR Initialization North Bridge Early Initialization South Bridge Early Initialization PCIE Training TPM Initialization SMBUS Early Initialization Clock Generator Initialization Memory Initial for Normal boot. Memory Initial for Crisis Recovery Simple Memory test Start to use Memory Chapter 4 153