Acer Aspire 5739G Acer Aspire 5739G Series Service Guide - Page 166

Code 0x26 0x27 0x28 0x29 0x30 0x31 0x32 0x33 0x34 0x35 0x43 Description Program the receive enable reference timing control register Program the DLL Timing Control Registers, RCOMP settings Enable DRAM Channel I/O Buffers Enable all clocks on populated rows Perform JEDEC memory initialization for all memory rows Perform steps required after memory init Program DRAM throttling and throttling event registers Setup DRAM control register for normal operation and enable Enable RCOMP Clear DRAM initialization bit in the SB Initialization Sequence Completed, program graphic clocks Program Thermal Throttling 156 Chapter 3