Acer Aspire 5750Z Acer Aspire 5350, 5750, 5750G, 5750Z Notebook Service Guide - Page 159

Post Codes 0 The following tables describe the POST codes and descriptions during the POST. Table 4-2. NO_EVICTION_MODE_DEBUG EQU 1 (CommonPlatform\sec\Ia32\SecCore.inc) Phase POST Code Range 0xC2 MTRR setup 0xC3 Enable cache 0xC4 Establish cache tags nf 0xC5 Enter NEM, Place the BSP in No Fill mode, set CR0.CD = 1, CR0.NW = 0. 0xCF Cache Init Finished Table 4-3. DEBUG_BIOS equ 1 (Chipset\Alviso\MemoryInitAsm\IA32\IMEMORY.INC) Phase POST Code Range 0xA0 First memory check point 0x01 Enable MCHBAR o 0x02 Check for DRAM initialization interrupt and reset fail 0x03 Verify all DIMMs are DDR or DDR2 and unbuffered 0x04 Detect an improper warm reset and handle eS 0x05 Detect if ECC SO-DIMMs are present in the system 0x06 Verify all DIMMs are single or double sided and not asymmetric 0x07 Verify all DIMMs are x8 or x16 width 0x08 Find a common CAS latency between the DIMMS and the MCH 0x09 Determine the memory frequency and CAS latency to program 0x22 Program the DRAM Bank Architecture register 0x23 Program the DRAM Timing & and DRAM Control registers 0x24 Program ODT 0x25 Perform steps required before memory init oft 0x26 Program the receive enable reference timing control register Program the DLL Timing Control Registers, RCOMP settings Se 0x27 Enable DRAM Channel I/O Buffers 0x28 Enable all clocks on populated rows 0x29 Perform JEDEC memory initialization for all memory rows 0x30 Perform steps required after memory init Troubleshooting 4-25