Biostar T41 HD Bios Setup - Page 34

Integrated Memory Test - led

Page 34 highlights

T41 HD BIOS Manual Integrated Memory Test Integrat ed Memory T est allows users to test memory module compatibilities without additional device or softw are. Step 1: T his item is disabled on default; change it to " Enable" to precede memory test. Main BIOS S ETUP UTILITY Advanced PCIPnP Boot Chips et T-Series Exit af ter overcloc king. OverC lock Navigato r [Normal] Automa te OverClock System Auto OverClock Sys tem [V6-Tech En gine] Manua l OverClock System Intel (R) SpeedStep (tm) tech Ratio CMOS Setting [Enabled] [ x9.0] CPU F requency Sett ing PCIE Frequency Set ting [200] [100] FSB(B sel) To North Bridge Latch [Auto] DRAM Frequency [Auto] > ALL Voltage Conf iguration Confi gure DRAM Tim ing by SPD [Enabled] > G.P .U Phase Cont rol Integ rated Memory Test [Enabled] Options Disa bled Enab led S elect Screen S elect Item En terG o to Sub Scr een F1 G eneral Help F1 0 S ave and Exit ES C E xit vxx.xx (C)C opyright 198 5-200x, Amer ican Megatre nds, Inc. Step 2: When the process is done, change the setting back from "Enabled" to "Disabled" to complete the test. Main BIOS S ETUP UTILITY Advanced PCIPnP Boot Chips et T-Series Exit af ter overcloc king. OverC lock Navigato r [Normal] Automa te OverClock System Auto OverClock Sys tem [V6-Tech En gine] Manua l OverClock System Intel (R) SpeedStep (tm) tech Ratio CMOS Setting [Enabled] [ x9.0] CPU F requency Sett ing PCIE Frequency Set ting [200] [100] FSB(B sel) To North Bridge Latch [Auto] DRAM Frequency [Auto] > ALL Voltage Conf iguration Confi gure DRAM Tim ing by SPD [Enabled] > G.P .U Phase Cont rol Integ rated Memory Test [Disabled] Options Disa bled Enab led S elect Screen S elect Item En terG o to Sub Scr een F1 G eneral Help F1 0 S ave and Exit ES C E xit vxx.xx (C)C opyright 198 5-200x, Amer ican Megatre nds, Inc. 33

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T41 HD BIOS Manual
33
Integrated Memory Test
Integrated Memory Test allows users to test memory module compatibilities without
additional device or software.
Step 1
:
This item is disabled on default; change it to “Enable” to precede memory test.
BIOS SETUP UTILITY
Main
Advanced
PCIPnP
Boot
Chipset
T-Series
vxx.xx (C)Copyright 1985-200x, American Megatrends, Inc.
Select Screen
Select Item
Go to Sub Screen
General Help
Save and Exit
Exit
Enter
F1
F10
ESC
=========== Automate OverClock System ===========
============ Manual OverClock System ============
after overclocking.
OverClock Navigator
[Normal]
> G.P.U Phase Control
Auto OverClock System
[V6-Tech Engine]
Intel(R) SpeedStep(tm) tech
[Enabled]
Ratio CMOS Setting
[ x9.0]
CPU Frequency Setting
[200]
PCIE Frequency Setting
[100]
FSB(Bsel) To NorthBridge Latch [Auto]
DRAM Frequency
[Auto]
> ALL Voltage Configuration
Configure DRAM Timing by SPD
[Enabled]
Integrated Memory Test
[Enabled]
Exit
Options
Disabled
Enabled
Step 2
:
When the process is done, change the setting back from “Enabled” to “Disabled” to
complete the test.
BIOS SETUP UTILITY
Main
Advanced
PCIPnP
Boot
Chipset
T-Series
vxx.xx (C)Copyright 1985-200x, American Megatrends, Inc.
Select Screen
Select Item
Go to Sub Screen
General Help
Save and Exit
Exit
Enter
F1
F10
ESC
=========== Automate OverClock System ===========
============ Manual OverClock System ============
after overclocking.
OverClock Navigator
[Normal]
> G.P.U Phase Control
Auto OverClock System
[V6-Tech Engine]
Intel(R) SpeedStep(tm) tech
[Enabled]
Ratio CMOS Setting
[ x9.0]
CPU Frequency Setting
[200]
PCIE Frequency Setting
[100]
FSB(Bsel) To NorthBridge Latch [Auto]
DRAM Frequency
[Auto]
> ALL Voltage Configuration
Configure DRAM Timing by SPD
[Enabled]
Integrated Memory Test
[Disabled]
Exit
Options
Disabled
Enabled