Foxconn A79A-S English Manual. - Page 40

3 This item is used to enable/disable memory remapping around memory hole. PCI doesn't actually care much which addresses are used, but by convention the PC platform puts them at the top of the 32-bit address space. For many years it wasn't possible or practical to put that much RAM into a PC. But now it is, so it's up to the memory controller and host bridge to figure out what to do. Many systems cause that high RAM to simply be ignored, resulting in the loss of effective RAM. More complex systems will take the RAM that would occupy that 3.5-4GB address space and re-map it into the 4.0-4.5 address space. The RAM doesn't care because it's just an array of storage cells, it's up to the memory controller to associate addresses with those storage cells. Of course, that only works if you're using a 64-bit (or 32bit physical address extension (PAE) enabled) OS that can deal with physical addresses larger than 32 bits. Once this option is enabled, the BIOS can see 4096MB of memory. ► DCT Unganged Mode DCT stands for DRAM Controller. Ganged refers to the use of both DRAM controllers within a memory controller acting in concert to access memory. For a description of ganged (128-bit DRAM data width) and unganged (64-bit DRAM data width) DRAM modes : Ganged channels (DDR2) : ■ DCT channels A and B can be ganged as a single logical 128-bit DIMM. ■ Offers highest DDR2 bandwidth. ■ Requires both DIMMs in a logical pair to have identical size and timing parameters, both DCTs programmed identically. Unganged channels ■ DCT channels A and B operate as two completely independent 64-bit channels (both chan- nels operate at the same frequency). ■ Reduce DRAM page conflicts - more concurrent open dram pages . ■ Better bus efficiency. Burst lengths supported When both DCTs are enabled in unganged mode, BIOS must initialize the frequency of each DCT in order. ► Power Down Enable This item is used to enable or disable the power down mode. A DIMM or a group of DIMMs enters power down mode by deasserting the corresponding clock enable signal when the DRAM controller detects that there are no transactions scheduled to any of the DIMMs connected to the clock enable signal. A DIMM or a group of DIMMs exits power down mode by asserting the corresponding clock enable signal when a transaction is scheduled to any DIMM connected to the clock enable signal. There are two CKE pins per DRAM channel. if all pages of the DRAMs associated with a CKE pin are closed, then these parts are placed in power down mode. ► Optimal Performance Mode This item is used to enable or disable the optimal performance mode for memory. ► Auto Tweak Performance Enables the DDR memory clocks to be tristated when alternate VID mode is enabled. ► DRAM Config_High Control This item is used to set the memory configuration. Options are [Auto] and [Manual]. 33