Foxconn P43AP English Manual. - Page 35

3 CPU Configuration CMOS Setup Utility - Copyright (C) 1985-2006, American Megatrends, Inc. CPU Configuration Configure advanced CPU settings Module Version:3F.11 Help Item Manufacturer : Intel It is available Pentium (R) Dual-Core CPU E5200 @ 2.50GHz only when the CPU Speed : 1.20GHz is not the XE CPU FSB Speed : 800MHz and EIST is enabled. Cache L1 :64 KB Cache L2 :2048 KB Ratio Status:Unlocked (Min:06, Max:12.5) Ratio Actual Value:6 Super Clock Free C1E Function Hardware Prefetcher Adjacent Cache Line Prefetch Limit CPUID MaxVal Execute Disable Bit Core Multi-Processing [Disabled] [Enabled] [Enabled] [Enabled] [Disabled] [Enabled] [Enabled] Move Enter:Select +/-/:Value F10:Save ESC:Exit F1:General Help F9:Optimized Defaults ► Super Clock Free When it is enabled, this item is used to adjust the multiplier of the CPU samples. ► C1E Function C1E represents Enhanced HALT State. It is a feature which Intel CPU uses to reduce power consumption when in halt state. C1E drops the CPU's multiplier and voltage to lower levels when a HLT (halt) command is issued. This item is used to enable/disable the C1E support. When disabled, the processor will only retrieve the currently requested cache line. ► Hardware Prefetcher The processor has a hardware prefetcher that automatically analyzes its requirements and prefetches data and instructions from the memory into the Level 2 cache that are likely to be required in the near future. This reduces the latency associated with memory reads. When enabled, the processor's hardware prefetcher will be enabled and allowed to automatically prefetch data and code for the processor. When disabled, the processor's hardware prefetcher will be disabled. ► Adjacent Cache Line Prefetcher (Appears only when CPU supports) The processor has a hardware adjacent cache line prefetch mechanism that automatically fetches an extra 64-byte cache line whenever the processor requests for a 64-byte cache line. This reduces cache latency by making the next cache line immediately available if the processor requires it as well. When enabled, the processor will retrieve the currently requested cache line, as well as the subsequent cache line. ► Limit CPUID MaxVal This item is used to enable or disable CPUID maximum value limit configuration. Set Limit CPUID MaxVal to 3, it should be [Disabled] for WinXP. ► Execute Disable Bit This item is used to enable/disable the Execute Disable Bit feature. Intel's Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow attacks when combined with a supporting operating system. 28