HP 381513-B21 HP Smart Array Controller technology, 3rd edition - Page 7
Mini SAS 4x cable connectors and receptacles, High-performance processor
UPC - 882780622029
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Mini SAS 4x cable connectors and receptacles Mini SAS 4x connectors and receptacles (Figure 2) are replacing SAS 4x connectors and receptacles in present generation Smart Array controllers. The ground pins in Mini SAS connectors can be used for power in active cables. Figure 2. The Mini SAS 4i connector (left) and receptacle (right) are replacing SAS 4x connectors and receptacles. For more detailed information on SAS technology and SAS-2 zoning, refer to the Serial Attached SCSI storage technology brief: http://h20000.www2.hp.com/bc/docs/support/SupportManual/c01613420/c01613420.pdf High-performance processor HP Smart Array controllers use a variety of high-performance processors for managing the RAID system. The Power PC and MIPS4 processors are the most widely used among Smart Array controllers. The PowerPC processor is a 64-bit processor based on reduced instruction set computer (RISC) technology. The processor connects to its internal peripherals using separate 128-bit-wide readand-write buses, each running at 133 MHz. Power PC processors have a highly pipelined architecture that allows dual instruction fetch, decode, and out-of-order issue, as well as out-of-order dispatch, execution, and completion. The Power PC flexibility features include independently configurable data cache arrays, write-back and write-through operation, and performance characteristics that increase cache memory allocation efficiency. Designed for extensive power management and maximum performance, Power PC processors provide increased throughput and a streamlined path to instruction completion, which means faster user access to data. The present generation Smart Array P410, P411, and P212 controllers use an embedded PM8011 SRC 8x6G 6Gb/s SAS RAID-on-Chip (RoC) MIPS processor. This reduced instruction set computing (RISC), instruction set architecture (ISA) processor operates at 600 MHz, has 34K instruction and data caches, and a 32-bit multi-threading I/O. The MIPS processor uses a 4-way set associative writeback, and flexible thread policy manager with programmable quality of service (QoS) support. 4 Microprocessor without Interlocked Pipeline Stages 7