HP DL360 ISS Technology Update, Volume 8, Number 4 - Page 3

ISS Technology Update Figure 1-2. Intel Nehalem architecture with NUMA Volume 8, Number 4 Understanding and optimizing memory performance in G6 servers With Intel Nehalem architecture, each processor has its own memory controller and three memory channels that it controls directly. In its fastest configuration, the new DDR3 memory used with these systems operates at 1333 Megatransfers per second. Since each transfer consists of 8 data bytes, the maximum raw throughput per memory channel can be easily calculated. 1333 MT/s x 8 Bytes per transfer = 10667 MB/s = 10.667 GB/s raw throughput per channel This is actually where the 10600 in PC3-10600 comes from, representing the maximum throughput for the DIMM in round numbers. Figure 1-3 shows both a physical and a logical block diagram of the Processor/Memory complex for a 2P ProLiant G6 system with 12 DIMM slots and 6 total memory channels. The key to optimizing system memory performance is to install memory so that it maximizes the number memory channels in use which maximizes the composite bandwidth. 3