HP ProLiant 3000 Highly Parallel System Architecture in Compaq Servers - Page 4

0166-0899-A TECHNOLOGY BRIEF (cont.) Highly Parallel System Architecture ... I/O SUBSYSTEM Compaq servers with the Highly Parallel System Architecture have dual peer-PCI buses to increase system I/O bandwidth. A single PCI bus provides I/O bandwidth of up to 133 MB/s (or 533MB/s for a 64/66 PCI bus), which must be shared by peripherals such as the SCSI controllers, array controllers, and a network interface controller. With dual-peer PCI buses, multiple requests can be processed in parallel. Each bus can provide peak bandwidth in parallel with the other controller, allowing an aggregate I/O bandwidth of up to 267 MB/s. This implementation provides twice the bandwidth of single bus architectures and reduces overall system latency to decrease system bottlenecks. The dual PCI buses also permit greater system I/O integration and expandability, supporting up to 12 PCI devices  twice the number supported on single bus implementations. This allows Compaq servers with the Highly Parallel System Architecture to integrate other PCI components, such as the SCSI and network controllers on the system board and still deliver up to eight available PCI-based I/O expansion slots. The dual peer-PCI buses are wide high-speed buses that support 64-Bit, 66-MHz PCI, and PCI Hot Plug I/O technology. Future enhancements from Compaq will allow the Highly Parallel System Architecture to support PCI-X technology. For more information about PCI-X, see technology brief ECG070/0299, PCI-X Technology: An Evolution of the PCI Bus. Another benefit of dual-peer PCI buses is the ability to balance system resources. Critical system resources reside on separate buses to help balance throughput and improve system efficiency: With peripherals divided between two PCI buses, there is less competition for access. This results in better performance. MEMORY ARCHITECTURE A new, standards-based memory architecture delivers significantly greater bandwidth and scalability by using dual memory controllers. While traditional memory architectures use a single memory controller to process all memory requests, the Highly Parallel System Architecture's dual memory controllers provide independently parallel, multipath access to memory from all processors and I/O devices. Each memory controller provides bandwidth of up to 800 MB/s. The aggregate peak bandwidth of up to 1.6 GB/s is two to four times that of other systems. Dual memory controllers permit up to 4 GB of error checking and correcting (ECC) SDRAM. This is the highest system memory capacity available on the market in an Intel-based, dual processor capable server. In addition, the 1-to-1 interleave memory scheme of the dual memory controllers allows customers the option of upgrading memory by one dual in-line memory module (DIMM) at a time, as opposed to the four DIMMs required in wider buses with 4-to-1 interleave schemes. Customers can purchase only as much memory as is required, making incremental upgrades to suit specific needs. The Highly Parallel System Architecture is a standards-based design that permits the use of thirdparty memory. However, Compaq has not tested and does not support third-party memory in its servers. ADVANCED SYMMETRIC MULTIPROCESSING The Highly Parallel System Architecture also supports symmetric multiprocessing (SMP), although the system-level parallelism is independent of the number of processors. SMP has been supported on RISC/UNIX servers for a number of years. Many people have not, however, associated Microsoft Windows NT and the applications that run on it with SMP. Windows NT does support SMP; and users can reap the benefits when running many demanding 4