IBM 4840-563 System Reference - Page 47
Interrupt Status Register B (Read Only) Offset 41h
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Interrupt Status Register B (Read Only) Offset 41h Bit 3 = Status of UART 3 Interrupt Status (0: No Interrupt, 1: Interrupt Asserted) Bit 2 = Status of UART 2 Interrupt Status (0: No Interrupt, 1: Interrupt Asserted) Bit 1 = Status of UART 1 Interrupt Status (0: No Interrupt, 1: Interrupt Asserted) Bit 0 = Status of UART 0 Interrupt Status (0: No Interrupt, 1: Interrupt Asserted) SurePOS 500 Model XX3 Technical Reference, v 1.3 81 Page 47 of
Interrupt Status Register B (Read Only) Offset 41h
Bit 3 = Status of UART 3 Interrupt Status (0: No Interrupt, 1: Interrupt Asserted)
Bit 2 = Status of UART 2 Interrupt Status (0: No Interrupt, 1: Interrupt Asserted)
Bit 1 = Status of UART 1 Interrupt Status (0: No Interrupt, 1: Interrupt Asserted)
Bit 0 = Status of UART 0 Interrupt Status (0: No Interrupt, 1: Interrupt Asserted)
SurePOS 500 Model XX3 Technical Reference, v 1.3
Page 47 of
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