Intel 945G User Manual - Page 34

Intel, 945G Express Chipset Development Kit User's Manual, Table 11, Port 80h POST Codes - sata

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Intel® 945G Express Chipset Development Kit User's Manual Setting Up the Development Kit Table 11 Range E0-FF / F0-FF E0 - EE EF boot/S3 Processor exception. Miscellaneous codes. Resume failure. Category/Subsystem Port 80h POST Codes POST Code Host Processor 10 11 12 13 Chipset 21 Memory 22 23 24 25 26 27 28 PCI Bus 50 51 52 53-57 USB 58 59 ATA/ATAPI/SATA 5A 5B SMBus 5C 5D Local Console 70 71 Description of POST Operation Power-on initialization of the host processor (boot strap processor). Host processor cache initialization (including APs). Starting application processor initialization. SMM initialization. Initializing a chipset component. Reading SPD from memory DIMMs. Detecting presence of memory DIMMs. Programming timing parameters in memory controller and DIMMs. Configuring memory. Optimizing memory settings. Initializing memory, such as ECC init. Testing memory. Enumerating PCI buses. Allocating resources to PCI bus. Hot Plug PCI controller initialization. Reserved for PCI bus. Resetting USB bus. Reserved for USB. Resetting PATA/SATA bus and all devices. Reserved for ATA. Resetting SMBUS. Reserved for SMBUS. Resetting the VGA controller. Disabling the VGA controller. 34 Reference #308823

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Intel
®
945G Express Chipset Development Kit User’s Manual
Setting Up the Development Kit
Reference #308823
34
Range
Category/Subsystem
E0–FF / F0–FF
Processor exception.
E0 – EE
Miscellaneous codes.
EF boot/S3
Resume failure.
Table 11
Port 80h POST Codes
POST Code
Description of POST Operation
Host Processor
10
Power-on initialization of the host processor (boot strap processor).
11
Host processor cache initialization (including APs).
12
Starting application processor initialization.
13
SMM initialization.
Chipset
21
Initializing a chipset component.
Memory
22
Reading SPD from memory DIMMs.
23
Detecting presence of memory DIMMs.
24
Programming timing parameters in memory controller and DIMMs.
25
Configuring memory.
26
Optimizing memory settings.
27
Initializing memory, such as ECC init.
28
Testing memory.
PCI Bus
50
Enumerating PCI buses.
51
Allocating resources to PCI bus.
52
Hot Plug PCI controller initialization.
53–57
Reserved for PCI bus.
USB
58
Resetting USB bus.
59
Reserved for USB.
ATA/ATAPI/SATA
5A
Resetting PATA/SATA bus and all devices.
5B
Reserved for ATA.
SMBus
5C
Resetting SMBUS.
5D
Reserved for SMBUS.
Local Console
70
Resetting the VGA controller.
71
Disabling the VGA controller.