Intel BOXD845BGSE Product Specification - Page 53

Table 17., PCI Interrupt Routing Map

Page 53 highlights

Technical Reference Table 17. PCI Interrupt Routing Map PCI Interrupt Source AGP connector ICH2 USB controller 1 SMBus controller ICH2 USB controller 2 ICH2 Audio/Modem ICH2 LAN OHCI controller 1 (Note 1) OHCI controller 2 (Note 1) EHCI controller (Note 1) PCI bus connector 1 PCI bus connector 2 PCI bus connector 3 PCI bus connector 4 (Note 2) PCI bus connector 5 (Note 2) PCI bus connector 6 (Note 2) Notes: 1. USB 2.0 option only 2. D845BG board only PIRQF INTB INTA INTD INTC INTB INTA INTB ICH2 PIRQ Signal Name PIRQG PIRQH PIRQB Other INTB INTA to PIRQA INTD to PIRQD INTB INTC INTB INTA to PIRQE INTA to PIRQC INTC INTB INTA INTD INTC INTB INTC INTC INTB INTA INTD INTC INTD INTD INTC INTB INTA INTD INTA ✏ NOTE In PIC mode, the ICH2 can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15). Typically, a device that does not share a PIRQ line will have a unique interrupt. However, in certain interrupt-constrained situations, it is possible for two or more of the PIRQ lines to be connected to the same IRQ signal. Refer to Table 16 for the allocation of PIRQ lines to IRQ signals in APIC mode. 53

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Technical Reference
53
Table 17.
PCI Interrupt Routing Map
ICH2 PIRQ Signal Name
PCI Interrupt Source
PIRQF
PIRQG
PIRQH
PIRQB
Other
AGP connector
INTB
INTA to PIRQA
ICH2 USB controller 1
INTD to PIRQD
SMBus controller
INTB
ICH2 USB controller 2
INTC
ICH2 Audio/Modem
INTB
ICH2 LAN
INTA to PIRQE
OHCI controller 1
(Note 1)
INTA to PIRQC
OHCI controller 2
(Note 1)
INTB
EHCI controller
(Note 1)
INTC
PCI bus connector 1
INTA
INTB
INTC
INTD
PCI bus connector 2
INTD
INTA
INTB
INTC
PCI bus connector 3
INTC
INTD
INTA
INTB
PCI bus connector 4
(Note 2)
INTB
INTC
INTD
INTA
PCI bus connector 5
(Note 2)
INTA
INTB
INTC
INTD
PCI bus connector 6
(Note 2)
INTB
INTC
INTD
INTA
Notes:
1.
USB 2.0 option only
2.
D845BG board only
NOTE
In PIC mode, the ICH2 can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6,
7, 9, 10, 11, 12, 14, and 15).
Typically, a device that does not share a PIRQ line will have a
unique interrupt.
However, in certain interrupt-constrained situations, it is possible for two or
more of the PIRQ lines to be connected to the same IRQ signal.
Refer to Table 16 for the
allocation of PIRQ lines to IRQ signals in APIC mode.