Intel BOXDH67CLB3 Product Guide - Page 48

Front Panel USB 2.0 Headers, S/PDIF Header, Table 12. USB 2.0 Header Signal Names

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Intel Desktop Board DH67CL Product Guide Front Panel USB 2.0 Headers Figure 20, G shows the location of the front panel USB 2.0 headers and Table 12 shows their pin assignments and signal names. Table 12. USB 2.0 Header Signal Names Pin Signal Name Pin 1 Power (+5 V) 2 3 D- 4 5 D+ 6 7 Ground 8 9 Key 10 Signal Name Power (+5 V) DD+ Ground No Connection NOTE Computer systems that have an unshielded cable attached to a USB port might not meet FCC Class B requirements, even if no device or a low-speed USB device is attached to the cable. Use a shielded cable that meets the requirements for a full-speed USB device. S/PDIF Header Figure 20, H shows the location of the S/PDIF output header. Table 13 shows the pin assignments and signal names for the S/PDIF output header. Table 13. S/PDIF Header Signal Names Pin Description 1 Ground 2 S/PDIF Out 3 Key (no pin) 4 +5 VDC 48

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Intel Desktop Board DH67CL Product Guide
48
Front Panel USB 2.0 Headers
Figure 20, G shows the location of the front panel USB 2.0 headers and Table 12
shows their pin assignments and signal names.
Table 12. USB 2.0 Header Signal Names
Pin
Signal Name
Pin
Signal Name
1
Power (+5 V)
2
Power (+5 V)
3
D-
4
D-
5
D+
6
D+
7
Ground
8
Ground
9
Key
10
No Connection
NOTE
Computer systems that have an unshielded cable attached to a USB port might not
meet FCC Class B requirements, even if no device or a low-speed USB device is
attached to the cable.
Use a shielded cable that meets the requirements for a
full-speed USB device.
S/PDIF Header
Figure 20, H shows the location of the S/PDIF output header.
Table 13 shows the pin
assignments and signal names for the S/PDIF output header.
Table 13. S/PDIF Header Signal Names
Pin
Description
1
Ground
2
S/PDIF Out
3
Key (no pin)
4
+5 VDC