Intel D925XCVLK Product Specification - Page 20

Intel Desktop Boards D925XCV/D925XBC Technical Product Specification 1.6 System Memory The boards have four DIMM sockets and support the following memory features: • 1.8 V (only) DDR2 SDRAM DIMMs • Unbuffered, single-sided or double-sided DIMMs with the following restriction: Double-sided DIMMS with x16 organization are not supported. • 4 GB maximum total system memory. Refer to Section 2.2.1 on page 55 for information on the total amount of addressable memory. • Minimum total system memory: 128 MB • Non-ECC DIMMs • Serial Presence Detect • DDR2 533 MHz or DDR2 400 MHz SDRAM DIMMs ✏ NOTES • Remove the PCI Express x16 video card before installing or upgrading memory to avoid interference with the memory retention mechanism. • To be fully compliant with all applicable DDR SDRAM memory specifications, the board should be populated with DIMMs that support the Serial Presence Detect (SPD) data structure. This allows the BIOS to read the SPD data and program the chipset to accurately configure memory settings for optimum performance. If non-SPD memory is installed, the BIOS will attempt to correctly configure the memory settings, but performance and reliability may be impacted or the DIMMs may not function under the determined frequency. Table 6 lists the supported DIMM configurations. Table 6. Supported Memory Configurations DIMM Capacity 128 MB 256 MB 256 MB 512 MB 512 MB Configuration SS SS SS DS SS SDRAM Density 256 Mbit 256 Mbit 512 Mbit 256 Mbit 512 Mbit SDRAM Organization Front-side/Back-side 16 M x 16/empty 32 M x 8/empty 32 M x 16/empty 32 M x 8/32 M x 8 64 M x 8/empty Number of SDRAM Devices 4 8 4 16 8 512 MB SS 1024 MB DS 1024 MB SS 2048 MB DS 1 Gbit 64 M x 16/empty 4 512 Mbit 64 M x 8/64 M x 8 16 1 Gbit 128 M x 8/empty 8 1 Gbit 128 M x 8/128 M x 8 16 Note: In the second column, "DS" refers to double-sided memory modules (containing two rows of SDRAM) and "SS" refers to single-sided memory modules (containing one row of SDRAM). # INTEGRATOR'S NOTE Refer to Section 2.2.1, on page 55 for additional information on available memory. 20