Intel DB65AL DB65AL Technical Product Specification - Page 21

SATA Interfaces

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Product Description 1.8 USB The board supports up to 12 USB 2.0 ports. The Intel B65 Express Chipset provides the USB controller for the 2.0 ports. The port arrangement is as follows: • Six USB 2.0 ports are implemented with stacked back panel connectors • Six USB 2.0 front panel ports implemented through three internal headers All 12 USB ports are high-speed, full-speed, and low-speed capable. NOTES Computer systems that have an unshielded cable attached to a USB port may not meet FCC Class B requirements, even if no device is attached to the cable. Use a shielded cable that meets the requirements for full-speed devices. For information about The location of the USB connectors on the back panel The location of the front panel USB headers Refer to Figure 9, page 44 Figure 10, page 45 1.9 SATA Interfaces The board provides six SATA connectors through the PCH, which support one device per connector: • One internal SATA 6 Gb/s port (blue) • Three internal SATA 3 Gb/s ports (black) • Two internal eSATA 3 Gb/s ports for external connectivity (red) The PCH provides independent SATA ports with a theoretical maximum transfer rate of 6 Gb/s for one port and 3 Gb/s for five ports. A point-to-point interface is used for host to device connections. The underlying SATA functionality is transparent to the operating system. The SATA controller can operate in both legacy and native modes. In legacy mode, standard IDE I/O and IRQ resources are assigned (IRQ 14 and 15). In Native mode, standard PCI Conventional bus resource steering is used. Native mode is the preferred mode for configurations using the Windows* XP, Windows Vista*, and Windows 7* operating systems. For more information, see: http://www.serialata.org/. For information about The location of the SATA connectors Refer to Figure 10, page 45 21

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Product Description
21
1.8
USB
The board supports up to 12 USB 2.0 ports. The Intel B65 Express Chipset provides
the USB controller for the 2.0 ports.
The port arrangement is as follows:
•
Six USB 2.0 ports are implemented with stacked back panel connectors
•
Six USB 2.0 front panel ports implemented through three internal headers
All 12 USB ports are high-speed, full-speed, and low-speed capable.
NOTES
Computer systems that have an unshielded cable attached to a USB port may not
meet FCC Class B requirements, even if no device is attached to the cable.
Use a
shielded cable that meets the requirements for full-speed devices.
For information about
Refer to
The location of the USB connectors on the back panel
Figure 9, page 44
The location of the front panel USB headers
Figure 10, page 45
1.9
SATA Interfaces
The board provides six SATA connectors through the PCH, which support one device
per connector:
•
One internal SATA 6 Gb/s port (blue)
•
Three internal SATA 3 Gb/s ports (black)
•
Two internal eSATA 3 Gb/s ports for external connectivity (red)
The PCH provides independent SATA ports with a theoretical maximum transfer rate of
6 Gb/s for one port and 3 Gb/s for five ports.
A point-to-point interface is used for
host to device connections.
The underlying SATA functionality is transparent to the operating system.
The SATA
controller can operate in both legacy and native modes.
In legacy mode, standard IDE
I/O and IRQ resources are assigned (IRQ 14 and 15).
In Native mode, standard PCI
Conventional bus resource steering is used. Native mode is the preferred mode for
configurations using the Windows* XP, Windows Vista*, and Windows 7* operating
systems.
For more information, see:
.
For information about
Refer to
The location of the SATA connectors
Figure 10, page 45