Intel I3-530 Specifications

Intel I3-530 Manual

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  • Intel I3-530 | Specifications - Page 1
    Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium Desktop Processor 6000 Series Specification Update January 2011 Reference Number: 322911-013
  • Intel I3-530 | Specifications - Page 2
    specific hardware and software you use. For more information including details on which processors support HT Technology, see http://www.intel.com/info/hyperthreading. 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers
  • Intel I3-530 | Specifications - Page 3
    Contents Contents Revision History ...5 Preface ...6 Summary Tables of Changes 8 Identification Information 14 Errata ...17 Specification Changes 49 Specification Clarifications 50 Documentation Changes 51 § 3 Specification Update
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    Contents 4 Specification Update
  • Intel I3-530 | Specifications - Page 5
    Erratum AAU32 added to this product Specification Update in error, all erratum details removed from the specification update document. -010 -011 -012 Updated Processor Identification table to include the SKU information for the Intel® Core™ i3-560 processor. Added Errata AAU103-AAU105 Added Errata
  • Intel I3-530 | Specifications - Page 6
    into the specification update and are no longer published in other documents. This document may also contain information that was not previously published. Affected Documents Document Title Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series
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    . Products are differentiated by their unique characteristics such as, core speed, L2 cache size, package type, etc. as described in the processor identification information table. Read all notes associated with each S-Spec number. Specification Changes are modifications to the current published
  • Intel I3-530 | Specifications - Page 8
    of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future is either new or modified from the previous version of the document. 8 Specification Update
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    Processor Instructions Greater than 15 Bytes May be Preempted General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation above 4-G Limit LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in 64-bit Mode MCi_Status Overflow Bit May Be Incorrectly Set
  • Intel I3-530 | Specifications - Page 10
    Processor is Hot, Then Re-enabling, May Result in Stuck Core specification update document. Delivery of Certain Events Immediately Following a VM Exit May Push a Corrupted RIP onto the Stack Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode Interrupt is Received while All Cores
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    May Overcount Rapid Core C3/C6 Transitions May Cause Unpredictable System Behavior APIC Timer CCR May Report 0 in Periodic Mode Performance Monitor Events INSTR_RETIRED and MEM_INST_RETIRED May Count Inaccurately A Page Fault May Not be Generated When the PS bit is set to "1" in a PML4E
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    Until the First Core C6 Transition Accesses to a VMCS May Not Operate Correctly If CR0.CD is Set on Any Logical Processor of a Core PCIe Port's LTSSM May Not Transition Properly in the Presence of TS1 or TS2 Ordered Sets That Have Unexpected Symbols Within those Sets 12 Specification Update
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    While Running Targeted Stress Graphics Workloads With Non-Matching Memory Configurations VM Entry May Omit Consistency Checks Related to Bit 14 (BS) of the Pending Debug Exception Field in Guest-State Area of the VMCS Intel Turbo Boost Technology Ratio Changes May Cause Unpredictable System Behavior
  • Intel I3-530 | Specifications - Page 14
    in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register. The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series can be identified by the following register contents: Stepping C-2 Vendor
  • Intel I3-530 | Specifications - Page 15
    Top-side Markings (Example) INTEL M ©'08 PROC# BRAND SLxxx [COO] SPEED/CACHE/FMB [FPO] e4 LOT NO S/N Table 1. Processor Identification (Sheet 1 of 2) S-Spec Number Processor Number Stepping Processor Signature Core Frequency (GHz) / DDR3 (MHz) / Integrated Graphics Frequency SLBTM i5-680
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    2 of 2) S-Spec Number Processor Number Stepping Processor Signature Core Frequency (GHz) / DDR3 (MHz) / Integrated Graphics Frequency SLBLR i3-530 C-2 20652h 2.93 / 1333 / 733 SLBMS SLBT6 G6950 G6960 C-2 20652h 2.80 / 1066 / 533 C-2 20652h 2.93 / 1066 / 533 Max Intel® Turbo Boost
  • Intel I3-530 | Specifications - Page 17
    section "Out- of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors" the processor performs REP MOVS or REP STOS as fast strings. Due to this erratum fast string REP MOVS/REP STOS instructions that cross page boundaries from WB/WC memory types to UC/WP/WT memory
  • Intel I3-530 | Specifications - Page 18
    bit 3] is set, a MOVD/MOVQ with MMX/XMM register operands may issue a memory load before getting the DNA exception. Workaround: Code which performs loads from memory that has side-effects can effectively workaround this behavior by using simple integer-based load instructions when 18 Specification
  • Intel I3-530 | Specifications - Page 19
    To/From Debug Registers Causes Debug Exception Problem: When in V86 mode, if a MOV instruction is executed to/from a debug registers, a general-protection exception (#GP) should be generated. However, in the case when the general detect enable flag (GD) bit is set, the observed behavior is that
  • Intel I3-530 | Specifications - Page 20
    are disabled at the start of the IRET. This erratum can only be observed with a software generated stack frame. Workaround: Software should not generate misaligned stack frames for use with IRET. Status: For the steppings affected, see the Summary Tables of Changes. 20 Specification Update
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    Store) and BTM (Branch Trace Message) mechanisms. However, during a specific boundary condition where the exception/interrupt occurs right after the execution of an instruction at the lower canonical boundary (0x00007FFFFFFFFFFF) in 64-bit mode, the LBR return registers will save a wrong return
  • Intel I3-530 | Specifications - Page 22
    bits of the CS segment register will have no impact unless software explicitly examines the CS segment register between enabling protected mode and the first FAR JMP. Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide of Changes. 22 Specification Update
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    Performance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately Problem: The performance monitor event SEGMENT_REG_LOADS (Event 06H) counts instructions is Set on a #GP Instruction Problem: While coming out of cold reset or exiting from C6, if the processor encounters an instruction longer
  • Intel I3-530 | Specifications - Page 24
    Changes. AAU25. Problem: IA32_MPERF Counter Stops Counting During On-Demand TM1 According to the Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide, the ratio of IA32_MPERF (MSR E7H) to IA32_APERF (MSR E8H) should reflect actual performance while TM1
  • Intel I3-530 | Specifications - Page 25
    is Pending May Cause an Unexpected Interrupt Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken on the new interrupt vector even if the mask bit is set. Implication: An interrupt may immediately be generated with the new vector when a LVT entry
  • Intel I3-530 | Specifications - Page 26
    and Referenced Data Structures Problem: Bits 53:50 of the IA32_VMX_BASIC MSR report the memory type that the processor uses to access the Implication: Memory ordering may be violated. Intel has not observed this erratum with any specification Update in error; all erratum details removed from the
  • Intel I3-530 | Specifications - Page 27
    instead of the expected one when the processor returns to C0. Implication: Due to this erratum, two interrupts may unexpectedly be generated by an xAPIC timer event. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 27 Specification Update
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    be blocked when core C6 is used during interrupt service routines. Intel has not instruction. When FREEZE_WHILE_SMM is set, a PEBS should not be generated until the event occurs outside of SMM. Implication: A PEBS record may be saved after an RSM instruction due to the associated performance
  • Intel I3-530 | Specifications - Page 29
    May Count Higher than Expected Problem: Performance Monitoring counter INST_RETIRED.STORES (Event: C0H) is used to track retired instructions which contain a store operation. Due to this erratum, the processor may also count other types of instructions including WRMSR and MFENCE. Implication
  • Intel I3-530 | Specifications - Page 30
    PAT. Intel has not observed this erratum with any commercially-available software or system. Workaround: Code pages should not be mapped with uncacheable and cacheable memory types at the same time. Status: For the steppings affected, see the Summary Tables of Changes. 30 Specification Update
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    Problem: Under certain circumstances, a general purpose performance counter, IA32_PMC0-4 (C1H - C4H), may count at core frequency or not count at all instead of counting the programmed event. Implication: The Performance MSR bit [9] is set to (OTHER_CORE_HIT_SNOOP) and bit [7] is set to
  • Intel I3-530 | Specifications - Page 32
    to non-writable without software performing an appropriate TLB invalidation. When a subsequent access to that address by a specific instruction (ADD, AND, BTC, BTR the value of IA32_MC3_STATUS.MSCOD if IA32_MC3_STATUS.OVER (bit [62]) is set. Workaround: None identified. Status: For the steppings
  • Intel I3-530 | Specifications - Page 33
    Core C3/C6 Transitions May Cause Unpredictable System Behavior Problem: Under a complex set of internal conditions, cores rapidly performing C3/C6 transitions in a system with Intel store instructions retired. However, due to this erratum, they may undercount. Implication: The performance monitor
  • Intel I3-530 | Specifications - Page 34
    AAU56. Problem: A Page Fault May Not be Generated When the PS bit is set to "1" in a PML4E or PDPTE On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7) is reserved in PML4Es and PDPTEs. If the translation of the linear address of a memory access encounters a PML4E or a
  • Intel I3-530 | Specifications - Page 35
    the IA32_FIXED_CTR2 overflows at the same time as any of the other performance counters. Implication: Multiple counter overflow interrupts may be unexpectedly generated. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 35 Specification Update
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    for the first branch after an EIST (Enhanced Intel® SpeedStep Technology) transition, T-states, C1E (C1 specific bit in the TSC (Time Stamp Counter) changes. (This specific bit is indicated by IA32_VMX_MISC bits [4:0] (0x485h) and has a value of 5 on the affected processors Specification Update
  • Intel I3-530 | Specifications - Page 37
    LIDT/LGDT/SIDT/SGDT Do Not Report Correct Operand Size Problem: When a VM exit occurs due to a LIDT, LGDT, SIDT, or SGDT instruction with a 32-bit operand, bit 11 of the VM-exit instruction information field should be set to 1. Due to this erratum, this bit is instead cleared to 0 (indicating a 16
  • Intel I3-530 | Specifications - Page 38
    the Summary Tables of Changes. AAU70. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions Problem: Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H) counts transitions from x87 Floating Point (FP) to MMX™ instructions. Due to this erratum, if only
  • Intel I3-530 | Specifications - Page 39
    MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations Problem: MSR_TURBO_RATIO_LIMIT MSR (1ADH) is designed to describe the maximum Intel Turbo Boost Technology potential of the processor. On some processors, a non-zero Intel Turbo Boost
  • Intel I3-530 | Specifications - Page 40
    Problem: If a performance monitoring counter overflows and causes a PMI (Performance Monitoring Interrupt) at the same time that the core enters C6, then this may cause the system to hang. Implication: Due to this erratum, the processor Intel may unexpectedly be generated by an Specification Update
  • Intel I3-530 | Specifications - Page 41
    a warm reset. Intel has not observed this erratum with any commercially available system. Workaround: A BIOS code change has been identified and may be implemented as a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. 41 Specification Update
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    should pull the PECI bus low to initiate a by a processor reset. Intel has not Problem: A synchronous SMI (System Management Interrupt) occurs as a result of an SMI generating I/O Write instruction and should be handled prior to the next instruction executing. Due to this erratum, the processor
  • Intel I3-530 | Specifications - Page 43
    Uses 32-Bit Address Size in 64-bit Mode Problem: The FP (Floating Point) Data Operand Pointer is the effective address of the operand associated with the last non-control FP instruction executed by the processor. If an 80bit FP access (load or store) uses a 32-bit address size in 64-bit mode and
  • Intel I3-530 | Specifications - Page 44
    in SMRAM State Save Area May Be Lost Problem: The IO_SMI bit (bit 0) in the IO state field at SMRAM offset 7FA4H is set to "1" by the processor to indicate a System Management Interrupt (SMI) is either taken immediately after a successful I/O instruction or is taken after a successful iteration of
  • Intel I3-530 | Specifications - Page 45
    processor may not meet the JEDEC DDR3 DRAM specification requirement that states: "CKE cannot be registered low twice within a tRFC(min) window". Intel to this specification Update in error; all erratum details removed from the specification update document. AAU99. Performance Monitor Events for
  • Intel I3-530 | Specifications - Page 46
    Processor of a Core Problem: The VMX (virtual-machine extensions) are controlled by the VMCS (virtual-machine control structure). If CR0.CD is set on any logical processor of a core, operations using the VMCS may not function correctly. Such operations include the VMREAD and VMWRITE instructions
  • Intel I3-530 | Specifications - Page 47
    Memory Configurations Problem: When the integrated graphics engine continuously generates a large stream of writes to system memory, and Intel Flex Memory Technology is enabled, with a different amount of memory in each channel, the memory arbiter may temporarily stop servicing other device
  • Intel I3-530 | Specifications - Page 48
    Problem: When Intel Turbo Boost Technology is enabled as determined by the TURBO_MODE_DISABLE bit being "0" in the IA32_MISC_ENABLES MSR (1A0H), the process of locking to new ratio may cause the processor to run with incorrect ratio settings Control Structure) instruction may erroneously overwrite
  • Intel I3-530 | Specifications - Page 49
    ® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 Datasheet - Volumes 1 and 2 • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A: Instruction Set
  • Intel I3-530 | Specifications - Page 50
    ® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 Datasheet - Volumes 1 and 2 • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A: Instruction Set
  • Intel I3-530 | Specifications - Page 51
    ® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 Datasheet - Volumes 1 and 2 • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A: Instruction Set
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Reference Number:
322911-013
Intel
®
Core
™
i5-600, i3-500
Desktop Processor Series and
Intel
®
Pentium Desktop
Processor 6000 Series
Specification Update
January 2011