Intel I3-530 Specifications - Page 34
BIST Results May be Additionally Reported After a GETSEC[WAKEUP]
View all Intel I3-530 manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 34 highlights
AAU56. Problem: A Page Fault May Not be Generated When the PS bit is set to "1" in a PML4E or PDPTE On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7) is reserved in PML4Es and PDPTEs. If the translation of the linear address of a memory access encounters a PML4E or a PDPTE with PS set to 1, a page fault should occur. Due to this erratum, PS of such an entry is ignored and no page fault will occur due to its being set. Implication: Software may not operate properly if it relies on the processor to deliver page faults when reserved bits are set in paging-structure entries. Workaround: Software should not set Bit 7 in any PML4E or PDPTE that has Present Bit (Bit 0) set to "1". Status: For the steppings affected, see the Summary Tables of Changes. AAU57. BIST Results May be Additionally Reported After a GETSEC[WAKEUP] or INIT-SIPI Sequence Problem: BIST results should only be reported in EAX the first time a logical processor wakes up from the Wait-For-SIPI state. Due to this erratum, BIST results may be additionally reported after INIT-SIPI sequences and when waking up RLP's from the SENTER sleep state using the GETSEC[WAKEUP] command. Implication: An INIT-SIPI sequence may show a non-zero value in EAX upon wakeup when a zero value is expected. RLP's waking up for the SENTER sleep state using the GETSEC[WAKEUP] command may show a different value in EAX upon wakeup than before going into the SENTER sleep state. Workaround: If necessary software may save the value in EAX prior to launching into the secure environment and restore upon wakeup and/or clear EAX after the INIT-SIPI sequence. Status: For the steppings affected, see the Summary Tables of Changes. AAU58. Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than Expected Problem: x87 instructions that trigger #MF normally service interrupts before the #MF. Due to this erratum, if an instruction that triggers #MF is executed while Enhanced Intel SpeedStep® Technology transitions, Intel® Turbo Boost Technology transitions, or Thermal Monitor events occur, the pending #MF may be signaled before pending interrupts are serviced. Implication: Software may observe #MF being signaled before pending interrupts are serviced. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 34 Specification Update