Intel P8700 Data Sheet

Intel P8700 - Core 2 Duo Processor Manual

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  • Intel P8700 | Data Sheet - Page 1
    Intel® Core™2 Duo Mobile Processor, Intel® Core™2 Solo Mobile Processor and Intel® Core™2 Extreme Mobile Processor on 45-nm Process Datasheet For platforms based on Mobile Intel® 4 Series Express Chipset Family March 2009 Document Number: 320120-004
  • Intel P8700 | Data Sheet - Page 2
    to obtain the latest specifications and before placing your product order. Φ 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for IntelÆ 64 architecture. Performance will vary depending on
  • Intel P8700 | Data Sheet - Page 3
    Information 51 4.1 Package Mechanical Specifications 51 4.2 Processor Pinout and Pin List 59 4.3 Alphabetical Signals Reference 93 5 Thermal Specifications and Design Considerations 101 5.1 Monitoring Die Temperature 108 5.1.1 Thermal Diode 108 5.1.2 Intel® Thermal Monitor 109 Datasheet
  • Intel P8700 | Data Sheet - Page 4
    Intel Core 2 Duo Mobile Processor in SFF Package Top View Lower Right Side 83 Tables 1 Coordination of Core Low-Power States at the Package Level 13 2 Voltage Identification Definition 26 3 BSEL[2:0] Encoding for BCLK Frequency 29 4 FSB Pin Groups ...30 5 Processor Absolute Maximum Ratings 31
  • Intel P8700 | Data Sheet - Page 5
    72 18 Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name 84 19 Signal Description ...93 20 Power Specifications for the Dual-Core Extreme Edition Processor 101 21 Power Specifications for the Dual-Core Standard Voltage Processor 102 22 Power Specifications for the Dual-Core Low
  • Intel P8700 | Data Sheet - Page 6
    18 - Added Table 23 - Added Table 24 - Added Table 25 August 2008 • Added information for Intel Core 2 Duo T9800, T9550, P9600, P8700 January 2009 • Added information for Intel Core 2 Duo processor skus below: - Updated Table 7 and 21 with T9900 - Updated Table 9 and 23 with SP9600 - Updated
  • Intel P8700 | Data Sheet - Page 7
    package (Power Optimized Performance-POP) • The Intel Core 2 Duo processor in SFF package supports the Mobile Intel® GS45 Express Chipset and Intel® ICH9M SFF I/O controller. This document contains electrical, mechanical and thermal specifications for: - Power Optimized Performance (POP) in SFF
  • Intel P8700 | Data Sheet - Page 8
    • Digital thermal sensor (DTS) • Intel® 64 architecture • Supports enhanced Intel® Virtualization Technology • Enhanced Intel® Dynamic Acceleration Technology and Enhanced Multi-Threaded Thermal Management (EMTTM) • Supports PSI2 functionality • SV processor offered in Micro-FCPGA and Micro-FCBGA
  • Intel P8700 | Data Sheet - Page 9
    in conjunction with Virtual Machine Monitor software, enables multiple, robust independent software environments inside a single platform. Half ratio support (N/2) for Core to Bus ratio TDP VCC VSS LV ULV DC-XE Intel Core 2 Duo processors and Intel Core 2 Extreme processors support the N/2 feature
  • Intel P8700 | Data Sheet - Page 10
    Introduction Document Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide Document Number 253667 253668 253669 NOTE: Contact your Intel representative for the latest revision of this document. § 10 Datasheet
  • Intel P8700 | Data Sheet - Page 11
    Control and Low-Power States The processor supports low-power states both at the individual core level and the package level for optimal power management. A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, C4, Intel® Enhanced Deeper Sleep and Intel® Deep Power Down Technology low
  • Intel P8700 | Data Sheet - Page 12
    Core state break HLT instruction C1/Auto Halt MWAIT(C1) Halt break C0 P_LVL2 or MWAIT(C2) Core State break Core † - STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4. ‡ - Core C4 state supports the package level Deep C4 sub-state. Ø - P_LVL5/P_LVL6 read is
  • Intel P8700 | Data Sheet - Page 13
    cause the processor to immediately initialize itself. A System Management Interrupt (SMI) handler will return execution to either Normal state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals, Volume 3A/3B: System Programmer's Guide for more
  • Intel P8700 | Data Sheet - Page 14
    to the C0 state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals, Volume 2A: Instruction Set Reference, A-M and Volume 2B: Instruction Set Reference, N-Z, for more information. Core C2 State Individual cores of the dual-core processor can enter the C2 state by initiating
  • Intel P8700 | Data Sheet - Page 15
    be deasserted after the deassertion of SLP# as per AC Specification T75. While in Stop-Grant state, the processor will service snoops and latch interrupts delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts and will service only one of each upon return to the Normal
  • Intel P8700 | Data Sheet - Page 16
    Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself,
  • Intel P8700 | Data Sheet - Page 17
    Intel Enhanced Deeper Sleep state: • The last core entering C4 issues a P_LVL4 or P_LVL5 I/O read or an MWAIT(C4) instruction and then progressively reduces the L2 cache to zero • Once the L2 cache has been reduced to zero, the processor triggers a special chipset sequence to notify the chipset
  • Intel P8700 | Data Sheet - Page 18
    conditions stated above still exist when the last core returns to C4 and the package enters Intel Enhanced Deeper Sleep state or Deep Power Down Technology state (C6), then the L2 will be shrunk to zero again. If a core requests a processor performance state resulting in a higher ratio than the
  • Intel P8700 | Data Sheet - Page 19
    bus protocol (BNR# mechanism) is used to block snooping. • Improved Intel® Thermal Monitor mode: - When the on-die thermal sensor indicates that the die temperature is too high the processor can automatically perform a transition to a lower frequency and voltage specified in a software-programmable
  • Intel P8700 | Data Sheet - Page 20
    the performance state of the processor by performing an Enhanced Intel bits to automatically promote package lowpower states to enhanced package low-power states. Extended Stop-Grant and Enhanced Deeper Sleep must be enabled via the BIOS for the processor to remain within specification. As processor
  • Intel P8700 | Data Sheet - Page 21
    processor operating frequency from the Enhanced Intel SpeedStep Technology performance states and achieve the Super Low Frequency Mode (Super LFM). This feature is supported 50% of the externally visible frequency. Both the processor and GMCH maintain a virtual BCLK signal (VBCLK) that is aligned to
  • Intel P8700 | Data Sheet - Page 22
    Technology The processor supports Intel Dynamic Acceleration Technology mode. The Intel Dynamic Acceleration Technology feature allows one core of the processor to operate at a higher frequency point when the other core is inactive and the operating system requests increased performance. This higher
  • Intel P8700 | Data Sheet - Page 23
    DC Specifications section for more details. VID-x The processor implements the VID-x feature for improved control of core voltage levels when the processor enters a reduced power consumption state. VID-x applies only when the processor is in the Intel Dynamic Acceleration Technology performance
  • Intel P8700 | Data Sheet - Page 24
    Low Power Features 24 Datasheet
  • Intel P8700 | Data Sheet - Page 25
    the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low-power states, should be provided by the voltage regulator solution depending on the specific system design. FSB AGTL+ Decoupling The processors integrate signal termination
  • Intel P8700 | Data Sheet - Page 26
    Electrical Specifications 3.3 Table 2. Voltage Identification and Power Sequencing The processor uses seven voltage identification pins,VID[6:0], to support automatic selection of power supply voltages. The VID pins for the processor are CMOS outputs driven by the processor VID circuitry. Table 2
  • Intel P8700 | Data Sheet - Page 27
    Electrical Specifications Table 2. Voltage Identification Definition (Sheet 2 of 3) VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0
  • Intel P8700 | Data Sheet - Page 28
    Electrical Specifications Table 2. Voltage Identification Definition (Sheet 3 of 3) VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
  • Intel P8700 | Data Sheet - Page 29
    Electrical Specifications 3.4 3.5 Catastrophic Thermal Protection The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of
  • Intel P8700 | Data Sheet - Page 30
    Electrical Specifications 3.7 Table 4. FSB Signal Groups The FSB signals have been combined into groups by buffer type in the following sections. In this document, the term "AGTL+
  • Intel P8700 | Data Sheet - Page 31
    always be taken to avoid high static voltages or electric fields. Processor Absolute Maximum Ratings Symbol Parameter TSTORAGE TSTORAGE VCC VinAGTL+ VinAsynch_CMOS Processor Storage Temperature Processor Storage Temperature Any Processor Supply Voltage with Respect to VSS AGTL+ Buffer DC Input
  • Intel P8700 | Data Sheet - Page 32
    refer to the processor case temperature specifications. 4. This rating applies to the processor and does not include any tray or packaging. 5. Failure to adhere to this specification can affect the long-term reliability of the processor. 6. For Intel® Core™2 Duo mobile processors in 22x22 mm
  • Intel P8700 | Data Sheet - Page 33
    the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State). 2. The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with a 100-MHz bandwidth oscilloscope
  • Intel P8700 | Data Sheet - Page 34
    (C6) ICC for Processors Recommended Design Target ICC for Processors Processor Number Core Frequency/Voltage ICC IAH, ISGNT T9900 T9800 T9600 T9550 T9400 3.06 GHz & VCCHFM 2.93 GHz & VCCHFM 2.80 GHz & VCCHFM 2.66 GHz & VCCHFM 2.53 GHz & VCCHFM 1.6 GHz & VCCLFM 0.8 GHz & VCCSLFM ICC Auto
  • Intel P8700 | Data Sheet - Page 35
    ICC for Processors - - - Processor Number Core Frequency/Voltage - - - P9700 P9600 ICC P8800 P9500 P8700 P8600 P8400 2.8 GHz & VCCHFM 2.667 GHz & VCCHFM 2.667 GHz & VCCHFM 2.53 GHz & VCCHFM 2.53 GHz & VCCHFM 2.4 GHz & VCCHFM 2.267 GHz & VCCHFM 1.6 GHz & VCCLFM 0.8 GHz & VCCSLFM 38
  • Intel P8700 | Data Sheet - Page 36
    the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State). 2. The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with a 100-MHz bandwidth oscilloscope
  • Intel P8700 | Data Sheet - Page 37
    Table 9. Voltage and Current Specifications for the Dual-Core, Power Optimized Performance (25 W) SFF Processors Symbol Parameter Min Typ Max Unit Notes VCCDAM VCC in Enhanced Intel® Dynamic Acceleration Technology Mode VCCHFM VCCLFM VCCSLFM VCC,BOOT VCCP VCCA VCCDPRSLP VDC4 VCCDPPWDN
  • Intel P8700 | Data Sheet - Page 38
    ICCDES. VR OCP threshold should be high enough to support current levels described herein. Table 10. Voltage and Current Specifications for the Dual-Core, Low-Voltage SFF Processor Symbol Parameter VCCDAM VCC in Enhanced Intel® Dynamic Acceleration Technology Mode VCCHFM VCCLFM VCCSLFM VCC
  • Intel P8700 | Data Sheet - Page 39
    the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State). 2. The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with a 100-MHz bandwidth oscilloscope
  • Intel P8700 | Data Sheet - Page 40
    Table 11. Voltage and Current Specifications for the Dual-Core, Ultra-Low-Voltage SFF Processor Symbol Parameter VCCDAM VCC in Enhanced Intel® Dynamic Acceleration Technology Mode VCCHFM VCCLFM VCCSLFM VCC,BOOT VCCP VCCA VCCDPRSLP VDC4 VCCDPPWDN ICCDES VCC at Highest Frequency Mode
  • Intel P8700 | Data Sheet - Page 41
    than maximum specified ICCDES. VR OCP threshold should be high enough to support current levels described herein. Table 12. Voltage and Current Specifications for the Ultra-Low-Voltage, Single-Core (5.5 W) SFF Processor Symbol Parameter VCCHFM VCCLFM VCCSLFM VCC,BOOT VCCP VCCA VCCDPRSLP VDC4
  • Intel P8700 | Data Sheet - Page 42
    Specifications for the Ultra-Low-Voltage, Single-Core (5.5 W) SFF Processor Symbol IDSLP IDPRSLP IDC4 IDPWDN dICC/DT ICCA ICCP Parameter ICC Deep Sleep HFM SuperLFM ICC Deeper Sleep ICC Intel Enhanced Deeper Sleep State ICC Deep Power Down Technology State (C6) VCC Power Supply Current Slew Rate
  • Intel P8700 | Data Sheet - Page 43
    Electrical Specifications Figure 4. Active VCC and ICC Loadline for Standard Voltage, Low-Power SV (25 W) and Dual-Core, Extreme Edition Processors VCC-CORE [V] VCC-CORE max {HFM|LFM} VCC-CORE, DC max {HFM|LFM} VCC-CORE nom {HFM|LFM} Slope = -2.1 mV/A at package VccSense, VssSense pins.
  • Intel P8700 | Data Sheet - Page 44
    Electrical Specifications Figure 5. Deeper Sleep VCC and ICC Loadline for Standard-Voltage, Low-Power SV (25 W) and Dual-Core Extreme Edition Processors VCC-CORE [V] VCC-CORE max {HFM|LFM} VCC-CORE, DC max {HFM|LFM} VCC-CORE nom {HFM|LFM} Slope = -2.1 mV/A at package VccSense, VssSense pins.
  • Intel P8700 | Data Sheet - Page 45
    Electrical Specifications Figure 6. Deeper Sleep VCC and ICC Loadline for Low-Power Standard-Voltage Processors VCC-CORE [V] VCC-CORE max {HFM|LFM} VCC-CORE, DC max {HFM|LFM} VCC-CORE nom {HFM|LFM} Slope = -4.0 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. 10mV=
  • Intel P8700 | Data Sheet - Page 46
    Electrical Specifications Figure 7. Active VCC and ICC Loadline for Low-Voltage, Ultra-Low-Voltage and Power Optimized Performance Processor VCC-CORE [V] VCC-CORE max {HFM|LFM} VCC-CORE, DC max {HFM|LFM} VCC-CORE nom {HFM|LFM} Slope = -4.0 mV/A at package VccSense, VssSense pins. Differential
  • Intel P8700 | Data Sheet - Page 47
    Electrical Specifications Figure 8. Deeper Sleep VCC and ICC Loadline for Low-Voltage, Ultra-Low-Voltage and Power Optimized Performance Processor VCC-CORE [V] VCC-CORE max {HFM|LFM} VCC-CORE, DC max {HFM|LFM} VCC-CORE nom {HFM|LFM} Slope = -4.0 mV/A at package VccSense, VssSense pins.
  • Intel P8700 | Data Sheet - Page 48
    . The VCCP referred to in these specifications is the instantaneous VCCP. 7. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at 0.31*VCCP. RTT is connected to VCCP on die. Refer to processor I/O buffer models for I/V characteristics. 8. Specified
  • Intel P8700 | Data Sheet - Page 49
    in this table apply to all processor frequencies. 2. The VCCP referred to in these specifications refers to instantaneous VCCP. 3. Measured at 0.1 *VCCP. 4. Measured at 0.9 *VCCP. 5. For Vin between 0 V and VCCP. Measured when the driver is tristated. 6. Cpad1 includes die capacitance
  • Intel P8700 | Data Sheet - Page 50
    Electrical Specifications 50 Datasheet
  • Intel P8700 | Data Sheet - Page 51
    risk due to uneven die pressure distribution under tilt, stack-up tolerances and other similar conditions. These specifications assume that a mechanical attach is designed specifically to load one type of processor. A 15-lbf load limit should not be exceeded on BGA packages so as to not impact
  • Intel P8700 | Data Sheet - Page 52
    Package Mechanical Specifications and Pin Information Figure 9. 6-MB and 3-MB on 6-MB Die Micro-FCPGA Package Drawing (Sheet 1 of 2) 52 B B1 478 PINS G1 H1 C2 C1 TOP
  • Intel P8700 | Data Sheet - Page 53
    Package Mechanical Specifications and Pin Information Figure 10. 3-MB die Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) Datasheet B B1 478 PINS G1 H1 C2 C1 TOP VIEW A FRONT 27 BASIC P 0.255 0.355 W 6g Keying Pins COMMENTS ø0.356 M C A B ø0.254 M C A1, A2 B6739-01 D76564(1) 53
  • Intel P8700 | Data Sheet - Page 54
    Package Mechanical Specifications and Pin Information Figure 11. 3-MB Die Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) 54 4X 7.00 4X 7.00 ø0.305±0.25 ø0.406 M C A B ø0.254 M C 13.97 6.985 1.625 1.625 13.97 6.985 EDGE KEEP OUT ZONE
  • Intel P8700 | Data Sheet - Page 55
    Package Mechanical Specifications and Pin Information Figure 12. 3-MB Die Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) Datasheet B B1 SEE DETAIL B 479 BALLS G1 H1 C2 C1 TOP VIEW SEE DETAIL A FRONT VIEW øM DETAIL B SCALE 50 B2 J2 A
  • Intel P8700 | Data Sheet - Page 56
    Package Mechanical Specifications and Pin Information Figure 13. 3-MB Die Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) 56 4X 7.00 4X 7.00 13.97 6.985 1.625 1.625 13.97 6.985 EDGE KEEP OUT ZONE 4X CORNER KEEP OUT
  • Intel P8700 | Data Sheet - Page 57
    Package Mechanical Specifications and Pin Information Figure 14. Intel Core 2 Duo Mobile Processor (POP and LV) Die Micro-FCBGA Processor Package Drawing Datasheet THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED,
  • Intel P8700 | Data Sheet - Page 58
    BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION. B1 B (C1) 0.203 A G1 H1 (C2) B2 A B6748-01 E38344(1) Package Mechanical Specifications and Pin Information Figure 15. Intel Core 2 Duo Mobile Processor (ULV SC and ULV DC) Die Micro-FCBGA
  • Intel P8700 | Data Sheet - Page 59
    Package Mechanical Specifications and Pin Information 4.2 Processor Pinout and Pin List Figure 16 and Figure 17 show the processor (SV and XE) pinout as viewed from the top of the package. Table 16 provides the pin list, arranged numerically by pin number. Figure 16
  • Intel P8700 | Data Sheet - Page 60
    Package Mechanical Specifications and Pin Information Figure 17. Processor Pinout (Top Package View, Right D[40]# VSS VSS W DSTBN[ 2]# Y DSTBP[ A 2]# A D[33]# D[47]# VSS A B VSS D[57]# D[53]# A C D[49]# VSS GTLREF A D D[48]# DSTBN[3] # VSS A E DSTBP[3] # VSS TEST4 A F 24
  • Intel P8700 | Data Sheet - Page 61
    Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Pin Name Pin # Signal Buffer Type Direction A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# A[17]# A[18]# A[19]# A[
  • Intel P8700 | Data Sheet - Page 62
    Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Pin Name Pin # Signal Buffer Type Direction BPRI# BR0# BSEL[0] BSEL[1] BSEL[2] COMP[0] COMP[1] COMP[2] COMP[3] D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[
  • Intel P8700 | Data Sheet - Page 63
    Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Pin Name Pin # Signal Buffer Type Direction D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# V23 T22 U25 U23
  • Intel P8700 | Data Sheet - Page 64
    Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Pin Name Pin # Signal Buffer Type Direction DSTBP[2]# AA26 DSTBP[3]# AF24 FERR Test Test Open Drain Output Power/ Other Power/ Other CMOS Input Common Clock Input CMOS Input Power/ Other 64 Datasheet
  • Intel P8700 | Data Sheet - Page 65
    Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Pin Name Pin # Signal Buffer Type Direction VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
  • Intel P8700 | Data Sheet - Page 66
    Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Pin Name Pin # Signal Buffer Type Direction VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
  • Intel P8700 | Data Sheet - Page 67
    Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Pin Name Pin # Signal Buffer Type Direction VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
  • Intel P8700 | Data Sheet - Page 68
    Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Pin Name Pin # Signal Buffer Type Direction VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
  • Intel P8700 | Data Sheet - Page 69
    Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Pin Name Pin # Signal Buffer Type Direction VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
  • Intel P8700 | Data Sheet - Page 70
    Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Pin Name Pin # Signal Buffer Type Direction VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
  • Intel P8700 | Data Sheet - Page 71
    Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Pin Name Pin # Signal Buffer Type Direction VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
  • Intel P8700 | Data Sheet - Page 72
    Package Mechanical Specifications and Pin Information Table 17. Pin # Listing Pin # Pin Name Signal Buffer Type Directi on A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
  • Intel P8700 | Data Sheet - Page 73
    Package Mechanical Specifications and Pin Information Table 17. Pin # Listing Pin # Pin Output D[63]# Source Synch Input/ Output VSS Power/Other D[57]# Source Synch Input/ Output D[53]# Source Synch Input/ Output BPM[2]# Common Clock Output VSS Power/Other Table 17. Pin # Listing
  • Intel P8700 | Data Sheet - Page 74
    Package Mechanical Specifications and Pin Information Table 17. Pin # Listing Pin # Pin Name Signal Buffer Type Directi on AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22
  • Intel P8700 | Data Sheet - Page 75
    Package Mechanical Specifications and Pin Information Table 17. Pin # Listing Pin # Pin Name Signal Buffer Type Directi on C8 C9 C10 C11 C12 C13 C14 C15 C16 C17
  • Intel P8700 | Data Sheet - Page 76
    Package Mechanical Specifications and Pin Information Table 17. Pin # Listing Pin # Pin Name Signal Buffer Type Directi on F2 F3 F4 F5 F6 F7 F8 F9 F10 F11
  • Intel P8700 | Data Sheet - Page 77
    Package Mechanical Specifications and Pin Information Table 17. Pin # Listing Pin # Pin Name Signal Buffer Type Directi on K3 K4 K5 K6 K21 K22 K23 K24 K25 K26
  • Intel P8700 | Data Sheet - Page 78
    Package Mechanical Specifications and Pin Information Table 17. Pin # Listing Pin # Pin Name Signal Buffer Type Directi on P26 R1 R2 R3 R4 R5 R6 R21 R22 R23
  • Intel P8700 | Data Sheet - Page 79
    Package Mechanical Specifications and Pin Information Table 17. Pin # Listing Pin # Pin Name Signal Buffer Type Directi on W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y6 Y21
  • Intel P8700 | Data Sheet - Page 80
    Package Mechanical Specifications and Pin Information Figure 18. Intel Core 2 Duo Mobile Processor in SFF Package Top View Upper Left Side BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH
  • Intel P8700 | Data Sheet - Page 81
    Package Mechanical Specifications and Pin Information Figure 19. Intel Core 2 Duo Mobile Processor in SFF Package Top View Upper Right Side AB AA Y W V U T R P N M L K J H G F E D C B A 1 A[7]# A[5]# REQ[2] # REQ[0] # LOCK# TRDY# DBSY# VSS VSS 2 A[15]# RSVD0 2 RSVD0 1 A[9]# A[3]#
  • Intel P8700 | Data Sheet - Page 82
    Package Mechanical Specifications and Pin Information Figure 20. Intel Core 2 Duo Mobile Processor in SFF 57]# D[45]# D[42]# D[43]# D[34]# D[35]# D[26]# 41 VSS D[60]# D[52]# D[51]# D[53]# D[46]# D[47]# DINV[2 ]# D[37]# TEST4 D[27]# 42 VSS VSS VSS VSS VSS VSS VSS VSS VSS
  • Intel P8700 | Data Sheet - Page 83
    Package Mechanical Specifications and Pin Information Figure 21. Intel Core 2 Duo Mobile Processor in SFF Package Top View Lower Right Side AB AA Y W V U T R P N M L K J H G F E D C B A 23 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 24 VCC VCC
  • Intel P8700 | Data Sheet - Page 84
    Package Mechanical Specifications and Pin Information Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball ]# D[43]# D[44]# D[45]# D[46]# D[47]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# R41 W41 N43 U41 AA41 AB40 AD40 AC41 AA43 Y40 Y44 T44 AP44 AR43 AH40 AF40 AJ43
  • Intel P8700 | Data Sheet - Page 85
    Package Mechanical Specifications and Pin Information Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name Signal Name Ball Number Signal Name Ball Number Signal Name Ball Number D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[
  • Intel P8700 | Data Sheet - Page 86
    Package Mechanical Specifications and Pin Information Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name Signal Name Ball Number Signal Name Ball Number Signal Name Ball Number VCC VCC VCC VCC VCC VCC
  • Intel P8700 | Data Sheet - Page 87
    Package Mechanical Specifications and Pin Information Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name Signal Name Ball Number Signal Name Ball Number Signal Name Ball Number VCC VCC VCC VCC VCC VCC
  • Intel P8700 | Data Sheet - Page 88
    Package Mechanical Specifications and Pin Information Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name Signal Name Ball Number Signal Name Ball Number Signal Name Ball Number VCCP VCCP VCCP VCCP VCCP VCCP
  • Intel P8700 | Data Sheet - Page 89
    Package Mechanical Specifications and Pin Information Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name Signal Name Ball Number Signal Name Ball Number Signal Name Ball Number VCCSENSE VID[0] VID[1] VID[2] VID[3] VID[4]
  • Intel P8700 | Data Sheet - Page 90
    Package Mechanical Specifications and Pin Information Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name Signal Name Ball Number Signal Name Ball Number Signal Name Ball Number VSS VSS VSS VSS VSS VSS
  • Intel P8700 | Data Sheet - Page 91
    Package Mechanical Specifications and Pin Information Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name Signal Name Ball Number Signal Name Ball Number Signal Name Ball Number VSS VSS VSS VSS VSS VSS
  • Intel P8700 | Data Sheet - Page 92
    Package Mechanical Specifications and Pin Information Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name Signal Name Ball Number Signal Name Ball Number Signal Name Ball Number VSS VSS VSS VSS VSS VSS
  • Intel P8700 | Data Sheet - Page 93
    ) is asserted, the processor masks physical address bit 20 (A20#) before processor's address wrap-around at the 1-MB boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an input/output write instruction
  • Intel P8700 | Data Sheet - Page 94
    is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. COMP[3:0] must be terminated on the system board using precision (1% tolerance) resistors. D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the
  • Intel P8700 | Data Sheet - Page 95
    Specifications the data bus signals if more than half the bits, within the covered group, would change level in chipset to reduce power on the processor data bus input buffers. The processor drives this pin during dynamic FSB frequency switching. DRDY# (Data Ready) is asserted by the data driver
  • Intel P8700 | Data Sheet - Page 96
    support of the feature and enable/disable information, refer to Volumes 3A and 3B of the Intel® 64 and IA-32 Architectures Software Developer's Manuals and the Intel® Processor Identification and CPUID Instruction signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until
  • Intel P8700 | Data Sheet - Page 97
    to request debug operation of the processor. As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been
  • Intel P8700 | Data Sheet - Page 98
    reached their proper specifications. On observing active RESET#, both FSB agents will deassert their outputs within two clocks. All processor straps must be clock signals to the bus and processor core units. If DPSLP# is asserted while in the Sleep state, the processor will exit the Sleep state and
  • Intel P8700 | Data Sheet - Page 99
    that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 125 °C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin. TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRDY# (Target
  • Intel P8700 | Data Sheet - Page 100
    . Conversely, the VR output must be disabled until the voltage supply for the VID pins becomes valid. The VID pins are needed to support the processor voltage specification variations. See Table 2 for definitions of these pins. The VR must supply the voltage that is requested by the pins, or disable
  • Intel P8700 | Data Sheet - Page 101
    for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed so the processor remains within the minimum and maximum junction temperature (TJ) specifications at the corresponding thermal design power (TDP) value listed
  • Intel P8700 | Data Sheet - Page 102
    Table 21. Power Specifications for the Dual-Core Standard Voltage Processor Symbol Processor Number Core Frequency & Voltage TDP T9900 T9800 T9600 T9550 T9400 3.06 GHz & VCCHFM 2.93 GHz & VCCHFM 2.80 GHz & VCCHFM 2.66 GHz & VCCHFM 2.53 GHz & VCCHFM 1.6 GHz & VCCLFM 0.8 GHz & VCCSLFM Symbol
  • Intel P8700 | Data Sheet - Page 103
    Specifications for the Dual-Core Low Power Standard Voltage Processors (25W) in Standard Package Symbol Processor Number Core Frequency & Voltage TDP P9700 P9600 P8800 P9500 P8700 P8600 P8400 2.8 GHz & VCCHFM 2.667 GHz & VCCHFM 2.667 GHz & VCCHFM 2.53 GHz & VCCHFM 2.53 GHz & VCCHFM 2.4 GHz
  • Intel P8700 | Data Sheet - Page 104
    Table 23. Power Specifications for the Dual-Core Power Optimized Performance (25 W) SFF Processors Symbol Processor Number Core Frequency & Voltage Thermal Design Power Unit Notes TDP Symbol PAH, PSGNT PSLP PDSLP PDPRSLP PDC4 PC6 TJ SP9600 SP9400 SP9300 2.53 GHz & HFM VCC 2.4 GHz & HFM VCC
  • Intel P8700 | Data Sheet - Page 105
    and Design Considerations Table 24. Power Specifications fro the Dual-Core Low Voltage (LV) SFF Processors Symbol TDP Processor Number SL9600 SL9400 SL9300 Core Frequency & Voltage 2.13 GHz & HFM VCC 1.86 GHz & HFM VCC 1.6 GHz & HFM VCC 1.6 GHz & Super LFM VCC 0.8 GHz & Super LFM VCC Symbol PAH
  • Intel P8700 | Data Sheet - Page 106
    100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor's automatic mode
  • Intel P8700 | Data Sheet - Page 107
    100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor's automatic mode
  • Intel P8700 | Data Sheet - Page 108
    Thermal Specifications and Design Considerations 5.1 Monitoring Die Temperature The processor incorporates three methods of monitoring die temperature: • Thermal Diode • Intel® Thermal Monitor • Digital Thermal Sensor 5.1.1 Table 27. Thermal Diode Intel's processors utilize an SMBus thermal
  • Intel P8700 | Data Sheet - Page 109
    Thermal Monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks or by initiating an Enhanced Intel SpeedStep Technology transition when the processor silicon reaches its maximum operating temperature. The Intel Thermal Monitor uses two modes to
  • Intel P8700 | Data Sheet - Page 110
    processor will perform an Enhanced Intel SpeedStep Technology transition to the LFM. When the processor temperature drops below the critical level, the processor will make an Enhanced Intel SpeedStep Technology transition to the last requested operating point. The processor also supports Enhanced
  • Intel P8700 | Data Sheet - Page 111
    is not ensured once the activation of the Out of Specification status bit is set. The DTS-relative temperature readout corresponds to the Thermal Monitor (TM1/TM2) trigger point. When the DTS indicates maximum processor core temperature has been reached, the TM1 or TM2 hardware thermal control
  • Intel P8700 | Data Sheet - Page 112
    interrupts via the core's local APIC. Refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals for specific register and programming details. Out of Specification Detection Overheat detection is performed by monitoring the processor temperature and temperature gradient. This
  • Intel P8700 | Data Sheet - Page 113
    Thermal Specifications and Design Considerations of time when running the most power-intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. § Datasheet 113
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Document Number: 320120-004
Intel® Core™2 Duo Mobile
Processor, Intel® Core™2 Solo
Mobile Processor and Intel® Core™2
Extreme Mobile Processor on 45-nm
Process
Datasheet
For platforms based on Mobile Intel® 4 Series Express Chipset Family
March 2009