Intel Q9300 Data Sheet

Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Manual

Get Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor PDF manuals and user guides
UPC - 675900938236
View all Intel Q9300 manuals
Add to My Manuals
Save this manual to your list of manuals

Intel Q9300 manual content summary:

  • Intel Q9300 | Data Sheet - Page 1
    Intel® Core™2 Extreme Processor QX9000Δ Series, Intel® Core™2 Quad Processor Q9000Δ, Q9000SΔ, Q8000Δ, and Q8000SΔ Series Datasheet - on 45 nm process in the 775 land package August 2009 Document Number: 318726-010
  • Intel Q9300 | Data Sheet - Page 2
    ® Core™2 Extreme processor QX9000 series and Intel® Core™2 Quad processor Q9000, Q9000S, Q8000, and Q8000S series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact
  • Intel Q9300 | Data Sheet - Page 3
    3.1 Package Mechanical Drawing 35 3.2 Processor Component Keep-Out Zones 39 3.3 Package Loading Specifications 39 3.4 Package Handling Guidelines 39 3.5 Package Insertion Specifications 40 3.6 Processor Mass Specification 40 3.7 Processor Materials 40 3.8 Processor Markings 40 4 Land Listing
  • Intel Q9300 | Data Sheet - Page 4
    Requirements 97 7.3.1 Fan Heatsink Power Supply 97 7.4 Thermal Specifications 99 7.4.1 Boxed Processor Cooling Requirements 99 7.4.2 Variable Speed Fan 100 7.5 Boxed Intel® Core™2 Extreme Processor QX9650 Specifications 101 7.5.1 Boxed Intel® Core™2 Extreme Processor QX9650 Fan Heatsink Weight
  • Intel Q9300 | Data Sheet - Page 5
    Profile 80 5-4 Intel® Core™2 Quad Processor Q9000S and Q8000S Series Thermal Profile 81 5-5 Case Temperature (TC) Measurement Location 82 5-6 Thermal Monitor 2 Frequency and Voltage Ordering 84 5-7 Conceptual Fan Control Diagram on PECI-Based Platforms 86 6-1 Processor Low Power State Machine
  • Intel Q9300 | Data Sheet - Page 6
    Intel® Core™2 Extreme Processor QX9650 Thermal Profile 79 5-4 Intel® Core™2 Quad Processor Q9000 and Q8000 Series Thermal Profile 80 5-5 Intel® Core™2 Quad Processor Q9000S and Q8000S Series Thermal Profile 81 5-6 GetTemp0() Error Codes 87 6-1 Power-On Configuration Option Signals 89 7-1 Fan
  • Intel Q9300 | Data Sheet - Page 7
    • Initial release • Added Intel® Core™2 Quad processors Q9550, Q9450, and Q9300 • Added 1600 MHz FSB • Added Intel® Core™2 Extreme processor QX9770 • Added Intel® Core™2 Quad processors Q9650 and Q9400 • Added PSI# signal • Updated Sections 6.2.3, 6.2.4, 6.2.5, 6.2.6, 6.2.7, and 6.3 • Updated FSB
  • Intel Q9300 | Data Sheet - Page 8
    8 Datasheet
  • Intel Q9300 | Data Sheet - Page 9
    Intel® Virtualization Technology (Intel® Core™2 Extreme processor QX9650, Intel® Core™2 Quad processor Q9000 and Q9000S series, Intel® Core™2 Quad processors Q8400 and Q8400S only) • Supports Intel® Trusted Execution Technology (Intel® Core™2 Quad processor Q9000 and Q9000S series only) • Low power
  • Intel Q9300 | Data Sheet - Page 10
    Intel Core™2 Extreme processor QX9000 series, Intel® Core™2 Quad processor Q9000 and Q9000S series, and Intel® Core™2 Quad processors Q8400 and Q8400S support Intel® Virtualization Technology. Virtualization Technology provides silicon-based functionality that works together with compatible Virtual
  • Intel Q9300 | Data Sheet - Page 11
    , the Intel® Core™2 Extreme processor QX9000 series, Intel® Core™2 Quad processor Q9000 and Q9000S series, and Intel® Core™2 Quad processors Q8400 and Q8400S support Intel® Virtualization Technology (Intel® VT). Further, the Intel® Core™2 Quad processor Q9000 and Q9000S series support Intel® Trusted
  • Intel Q9300 | Data Sheet - Page 12
    the processor and system core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O. Processor Terminology Definitions Commonly used terms are explained here for clarification: • Intel® Core™2 Extreme processor QX9000 series - Quad core Extreme
  • Intel Q9300 | Data Sheet - Page 13
    trade-offs to be made between performance and power consumptions, based on processor utilization. This may lower average power consumption (in conjunction with OS support). • Intel® Virtualization Technology (Intel® VT) - A set of hardware enhancements to Intel server and client platforms that can
  • Intel Q9300 | Data Sheet - Page 14
    Specification Update Intel® Core™2 Extreme Processor and Intel® Core™2 Quad Processor Thermal and Mechanical Design Guidelines Intel® Core™2 Extreme Processor QX6800 and Intel® Core™2 Extreme Processor QX9770 Thermal and Mechanical Design Guidelines Voltage Regulator-Down (VRD) 11.0 Processor Power
  • Intel Q9300 | Data Sheet - Page 15
    Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket. VTT Decoupling Decoupling must be provided on the motherboard. Decoupling solutions must be sized to meet the expected load. To ensure compliance with the specifications, various factors associated with
  • Intel Q9300 | Data Sheet - Page 16
    ® Core™2 Extreme Processor QX9000 Series and Intel® Core™2 Quad Processor Q9000, Q9000S, Q8000, and Q8000S Series Specification Update for further details on specific valid core frequency and VID values of the processor. Note that this differs from the VID employed by the processor during a power
  • Intel Q9300 | Data Sheet - Page 17
    Electrical Specifications Table 2-1. Voltage Identification Definition VID VID VID VID VID VID VID VID 76543210 Voltage 00000000 OFF 00000010 1.6 0 0 0 0 0 1 0 0 1.5875 0 0 0 0 0 1 1 0 1.575 0 0 0 0 1 0 0 0 1.5625 00001010 1.55 0 0 0 0 1 1 0 0 1.5375 0 0 0 0 1 1 1 0 1.525 0 0 0 1 0 0
  • Intel Q9300 | Data Sheet - Page 18
    40 Ω and 60 Ω should be used. Power Segment Identifier (PSID) Power Segment Identifier (PSID) is a mechanism to prevent booting under mismatched power requirement situations. The PSID mechanism enables BIOS to detect if the processor in use requires more power than the platform voltage regulator (VR
  • Intel Q9300 | Data Sheet - Page 19
    Maximum and Minimum Ratings Symbol Parameter Min VCC Core voltage with respect to VSS -0.3 VTT FSB termination voltage with respect to VSS -0.3 TCASE Processor case temperature See Section 5 TSTORAGE Processor storage temperature -40 Max 1.45 1.45 See Section 5 85 Unit Notes1
  • Intel Q9300 | Data Sheet - Page 20
    Specification Table 2-3. Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes2, 10 VID Range VCC Core VCC_BOOT VCCPLL VID 0.8500 - 1.3625 V Processor Number V QX9770 3.20 GHz (12 MB Cache) Processor Q9400S 2.66 GHz (6 MB Cache) Q9300 2.50 GHz (6 MB Cache) Q8400
  • Intel Q9300 | Data Sheet - Page 21
    range. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep® Technology, or Extended HALT State). 2. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical
  • Intel Q9300 | Data Sheet - Page 22
    line. Refer to the Voltage Regulator Design Guide to determine the total ITT drawn by the system. This parameter is based on design characterization and is not tested. 10. Adherence to the voltage specifications for the processor are required to ensure reliable processor operation. 22 Datasheet
  • Intel Q9300 | Data Sheet - Page 23
    156 125 -0.163 -0.184 -0.191 -0.212 -0.219 NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Design Guide for socket loadline guidelines and
  • Intel Q9300 | Data Sheet - Page 24
    except for overshoot allowed as shown in Section 2.6.3. 2. This loadline specification shows the deviation from the VID set point. 3. The loadlines circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Design Guide for socket loadline guidelines and VR
  • Intel Q9300 | Data Sheet - Page 25
    Electrical Specifications 2.6.3 VCC Overshoot The processor can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage).
  • Intel Q9300 | Data Sheet - Page 26
    used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the motherboard (see Table 2-13 for GTLREF specifications). Termination resistors (RTT) for GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel chipsets Type
  • Intel Q9300 | Data Sheet - Page 27
    Specifications Table 2-6. FSB Signal Groups (Sheet 2 of 2) Signal Group Type Signals1 GTL+ Strobes CMOS Open Drain Output Open Drain Input/Output FSB Clock Power . 2. In processor systems where no debug port is implemented on the system board, these signals are used to support a debug port
  • Intel Q9300 | Data Sheet - Page 28
    timing requirements for entering and leaving the low power states. 2.7.3 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise
  • Intel Q9300 | Data Sheet - Page 29
    Control Interface (PECI) DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors, chipsets, and external thermal monitoring devices. The processor contains Digital Thermal Sensors (DTS) distributed throughout die. These
  • Intel Q9300 | Data Sheet - Page 30
    max specifications. Refer to Table 2-3 for VTT specifications. 2. The leakage specification applies to powered devices on the PECI bus. 3. The input buffers use Front Side Bus Specifications In most cases, termination resistors are not required as these are integrated into the processor silicon. See
  • Intel Q9300 | Data Sheet - Page 31
    7.5 and 13.5 (see Table 2-14 for the processor supported ratios). The processor uses a differential clocking implementation. For more information on the processor clocking, contact your Intel field representative. Table 2-14. Core Frequency to FSB Multiplier Configuration Multiplication of System
  • Intel Q9300 | Data Sheet - Page 32
    with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency. The Intel® Core™2 Extreme processor QX9650, Intel® Core™2 Quad processor Q9000, Q9000S, Q8000, and Q8000S series operate at a 1333 MHz
  • Intel Q9300 | Data Sheet - Page 33
    # falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 7. Duty - 5 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor core frequencies based on a 333 MHz BCLK[1:0]. 2.
  • Intel Q9300 | Data Sheet - Page 34
    Electrical Specifications . Figure 2-3. Differential Clock Waveform Threshold Region Tph BCLK1 VCROSS (ABS) VCROSS (ABS) Ringback Margin BCLK0 Tpl Tp Tp = T1: BCLK[1:0] period T2: BCLK[1:0] period stability (
  • Intel Q9300 | Data Sheet - Page 35
    Package Mechanical Specifications 3 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated
  • Intel Q9300 | Data Sheet - Page 36
    Figure 3-2. Processor Package Drawing (Sheet 1 of 3) Package Mechanical Specifications 36 Datasheet
  • Intel Q9300 | Data Sheet - Page 37
    Package Mechanical Specifications Figure 3-3. Processor Package Drawing (Sheet 2 of 3) Datasheet 37
  • Intel Q9300 | Data Sheet - Page 38
    Figure 3-4. Processor Package Drawing (Sheet 3 of 3) Package Mechanical Specifications 38 Datasheet
  • Intel Q9300 | Data Sheet - Page 39
    system or component testing should not exceed the maximum limits. The processor package substrate should not be used as a mechanical reference or load-bearing surface for thermal and mechanical solution. The minimum loading specification must be maintained by any thermal and mechanical solutions
  • Intel Q9300 | Data Sheet - Page 40
    3-5 and Figure 3-6 show the topside markings on the processor. This diagram is to aid in the identification of the processor. Figure 3-5. Processor Top-Side Markings Example (Intel® Core™2 Extreme Processor QX9650) INTEL M ©'06 QX9650 INTEL® CORE™2 EXTREME SLAN3 XXXX 3.00GHZ/2M/1333/05B [FPO](ee4
  • Intel Q9300 | Data Sheet - Page 41
    Package Mechanical Specifications Figure 3-6. Processor Top-Side Markings Example (Intel® Core™2 Quad Processor Q9000 Series) INTEL M ©'06 Q9550 INTEL® CORE™2 Quad SLAN3 XXXX 2.83GHZ/2M/1333/05A [FPO](ee4 4) ATPO S/N Datasheet 41
  • Intel Q9300 | Data Sheet - Page 42
    the document to identify processor lands. Processor Land Coordinates and Quadrants, Top View V CC / V SS 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V Socket 775 U T Quadrants R P Top
  • Intel Q9300 | Data Sheet - Page 43
    and Signal Descriptions 4 4.1 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 4-1 and Figure 4-2. These
  • Intel Q9300 | Data Sheet - Page 44
    Land Listing and Signal Descriptions Figure 4-1.land-out Diagram (Top View - Left Side) 30 29 28 AN VCC VCC VSS AM VCC VCC VSS AL VCC VCC VSS AK VSS VSS VSS AJ VSS VSS VSS AH VCC VCC VCC AG VCC VCC VCC AF VSS VSS VSS AE VSS VSS VSS AD VCC VCC VCC AC VCC VCC VCC AB VSS VSS VSS AA VSS VSS
  • Intel Q9300 | Data Sheet - Page 45
    Land Listing and Signal Descriptions Figure 4-2.land-out Diagram (Top View - Right Side) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS
  • Intel Q9300 | Data Sheet - Page 46
    Input/Output Table 4-1. Alphabetical Land Assignments Land Name Land # Signal Buffer Type Direction BPMb0# BPMb1# BPMb2# BPMb3# BPRI# BR0# BSEL0 BSEL1 BSEL2 COMP0 Asynch CMOS Output Power/Other Input Power/Other Input Power/Other Input Power/Other Input Power/Other Input Source
  • Intel Q9300 | Data Sheet - Page 47
    Signal Buffer Type Direction DSTBP0 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other FC31 FC32 J16 H15 Power/Other Power/Other FC33 FC34 H16 J17 Power/Other Power
  • Intel Q9300 | Data Sheet - Page 48
    TAP TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Input Input Output Input Input Input Input Input Input Output Output Input Input Input Input Input Input Table 4-1. Alphabetical Land Assignments Land Name Land # Signal Buffer Type TESTHI5 TESTHI6
  • Intel Q9300 | Data Sheet - Page 49
    AJ22 AJ25 AJ26 AJ8 AJ9 AK11 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 4-1. Alphabetical Land Assignments Land Name Land # Signal Buffer Type VCC VCC VCC VCC VCC
  • Intel Q9300 | Data Sheet - Page 50
    Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 4-1. Alphabetical Land Assignments Land Name Land # Signal Buffer Type
  • Intel Q9300 | Data Sheet - Page 51
    # Signal Buffer Type VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AB7 AC3 AC6 AC7 AD4 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other VSS
  • Intel Q9300 | Data Sheet - Page 52
    Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 4-1. Alphabetical Land Assignments Land Name Land # Signal Buffer Type
  • Intel Q9300 | Data Sheet - Page 53
    H8 H9 J4 J7 K2 K5 K7 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 4-1. Alphabetical Land Assignments Land Name Land # Signal Buffer Type VSS VSS VSS VSS VSS VSS VSS
  • Intel Q9300 | Data Sheet - Page 54
    Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Output Output Table 4-1. Alphabetical Land Assignments Land Name Land # Signal Buffer Type
  • Intel Q9300 | Data Sheet - Page 55
    VCC VCC Power/Other Power/Other Power/Other TAP Power/Other Power/Other Input Output Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input/Output Table 4-2. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction
  • Intel Q9300 | Data Sheet - Page 56
    Synch Input/Output Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Table 4-2. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22
  • Intel Q9300 | Data Sheet - Page 57
    VCC VSS VCC VCC TAP Asynch CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Output Table 4-2. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction AK16 AK17 AK18 AK19 AK20 AK21
  • Intel Q9300 | Data Sheet - Page 58
    Name Signal Buffer Type AM2 VID0 Asynch CMOS AM3 VID2 Asynch CMOS AM4 VSS Power/Other AM5 VID6 Asynch CMOS AM6 FC40 Power/Other AM7 VID7 Asynch CMOS AM8 VCC Power/Other AM9 VCC Power/Other AM10 VSS Power/Other AM11 VCC Power/Other AM12 VCC Power/Other AM13 VSS
  • Intel Q9300 | Data Sheet - Page 59
    Signal Buffer Type Direction C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 D1 D2 DBI3# D58# VSS VCCIOPLL VSS VTT VTT VTT VTT VTT VTT RESERVED ADS# Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input/Output
  • Intel Q9300 | Data Sheet - Page 60
    /Other F20 D41# Source Synch Input/Output F21 D43# Source Synch Input/Output F22 VSS Power/Other F23 RESERVED F24 TESTHI7 Power/Other Input Table 4-2. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction F25 F26 F27 F28 F29 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12
  • Intel Q9300 | Data Sheet - Page 61
    Signal Buffer Type Direction H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 VSS VSS VSS FC32 FC33 VSS VSS VSS VSS VSS VSS VSS VSS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other H25
  • Intel Q9300 | Data Sheet - Page 62
    Asynch CMOS A08# Source Synch VSS Power/Other ADSTB0# Source Synch VSS Power/Other VCC Power/Other Input Input Input Input Input Input/Output Input Output Input/Output Input/Output Table 4-2. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction R23 R24 R25 R26 R27
  • Intel Q9300 | Data Sheet - Page 63
    Name Signal Buffer Type Direction V7 VSS Power/Other V8 VCC Power/Other V23 VSS Power/Other V24 VSS Power/Other V25 VSS Power/Other V26 VSS Power/Other V27 VSS Power/Other V28 VSS Power/Other V29 VSS Power/Other V30 VSS Power/Other W1 MSID0 Power/Other W2 TDI_M
  • Intel Q9300 | Data Sheet - Page 64
    ADSTB[1:0]# Type Input/ processor's address wrap-around at the 1-MB boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction Block Next Request) is used to assert a bus stall
  • Intel Q9300 | Data Sheet - Page 65
    agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by de-asserting BPRI#. BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this signal is sampled to determine the agent ID = 0. This
  • Intel Q9300 | Data Sheet - Page 66
    ) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals
  • Intel Q9300 | Data Sheet - Page 67
    must be deasserted. Use of the DPRSTP# pin, and corresponding low power state, requires chipset support and may not be available on all platforms. NOTE:Some processors may not have the Deeper Sleep State enabled, refer to the Specification Update for specific sku and stepping guidance. DPSLP#, when
  • Intel Q9300 | Data Sheet - Page 68
    of support of the feature and enable/disable information, refer to volume 3 of the Intel Architecture Software Developer's Manual and the Intel Processor Identification and the CPUID Instruction application note. GTLREF[3:0] determine the signal reference level for GTL+ input signals. GTLREF is used
  • Intel Q9300 | Data Sheet - Page 69
    remain active until the system de-asserts PROCHOT#. See Section 5.2.4 for more details. Processor Power Status Indicator Signal. This signal may be asserted when the processor is in the Deeper Sleep State. PSI# can be used to improve load efficiency of the voltage regulator, resulting in platform
  • Intel Q9300 | Data Sheet - Page 70
    they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. The PWRGOOD signal must be supplied to the processor; it is used to protect
  • Intel Q9300 | Data Sheet - Page 71
    to the Deep Sleep state. Use of the SLP# pin, and corresponding low power state, requires chipset support and may not be available on all platforms. NOTE: Some processors may not have the Sleep State enabled, refer to the Specification Update for specific sku and stepping guidance. SMI# (System
  • Intel Q9300 | Data Sheet - Page 72
    . It may be left as a No-Connect on boards supporting the processor. VCCPLL provides isolated power for internal processor FSB PLLs. VCC_SENSE is an isolated low impedance connection to processor core power (VCC). It can be used to sense or measure voltage near the silicon with little noise
  • Intel Q9300 | Data Sheet - Page 73
    used to support automatic selection of power supply voltages (VCC). Refer to the Voltage Regulator Design Guide for more information. The voltage supply for these signals must be valid before the VR can supply VCC to the processor needed to support the processor voltage specification variations. See
  • Intel Q9300 | Data Sheet - Page 74
    Land Listing and Signal Descriptions 74 Datasheet
  • Intel Q9300 | Data Sheet - Page 75
    that do not alter the fan speed only need to ensure the case temperature meets the thermal profile specifications. In order to determine a processor's case temperature specification based on the thermal profile, it is necessary to accurately measure processor power dissipation. Intel has developed
  • Intel Q9300 | Data Sheet - Page 76
    Thermal Specifications and Design Considerations The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that
  • Intel Q9300 | Data Sheet - Page 77
    45.6 62 45.9 64 46.1 66 46.4 Power Maximum (W) Tc (°C) 68 46.6 70 46.9 72 47.2 74 47.4 76 47.7 78 47.9 80 48.2 82 48.5 84 48.7 86 49.0 88 49.2 90 49.5 92 49.8 94 50.0 96 50.3 98 50.5 100 50.8 Figure 5-1. Intel® Core™2 Extreme Processor QX9770 Thermal Profile
  • Intel Q9300 | Data Sheet - Page 78
    58.7 98 59.1 100 59.4 Power Maximum (W) Tc (°C) 102 59.7 104 60.1 106 60.4 108 60.8 110 61.1 112 61.4 114 61.8 116 62.1 118 62.5 120 62.8 122 63.1 124 63.5 126 63.8 128 64.2 130 64.5 Figure 5-2. Intel® Core™2 Extreme Processor QX9650 Thermal Profile Tcase (C) 65
  • Intel Q9300 | Data Sheet - Page 79
    Thermal Specifications and Design Considerations Table 5-4. Intel® Core™2 Quad Processor Q9000 and Q8000 Series Thermal Profile Power Maximum (W) Tc (°C) 0 44.8 2 45.4 4 45.9 6 46.5 8 47.0 10 47.6 12 48.2 14 48.7 16 49.3 18 49.8 20 50.4 22 51.0 24 51.5 Power Maximum (W)
  • Intel Q9300 | Data Sheet - Page 80
    Thermal Specifications and Design Considerations Table 5-5. Intel® Core™2 Quad Processor Q9000S and Q8000S Series Thermal Profile Power Maximum (W) Tc (°C) 0 49.6 2 50.4 4 51.2 6 52.1 8 52.9 10 53.7 12 54.5 14 55.3 16 56.2 Power Maximum (W) Tc (°C) 18 57.0 20 57.8 22 58.6
  • Intel Q9300 | Data Sheet - Page 81
    reaches its maximum operating temperature. The TCC reduces processor power consumption by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor feature must be enabled for the processor to be operating within specifications. The temperature at which Thermal
  • Intel Q9300 | Data Sheet - Page 82
    drivers, or interrupt handling routines. Thermal Monitor 2 The processor also supports an additional power reduction capability known as Thermal Monitor 2. This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor
  • Intel Q9300 | Data Sheet - Page 83
    P_CNT Control Register (located in the processor IA32_THERM_CONTROL MSR) is written to a '1', the processor will immediately reduce its power consumption via modulation (starting and stopping) of the internal core clock, independent of the processor temperature. When using On-Demand mode, the duty
  • Intel Q9300 | Data Sheet - Page 84
    must be designed to ensure the processor remains within specification. If the processor enters one of the above low-power states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the low-power state and the processor DTS temperature drops below the thermal trip
  • Intel Q9300 | Data Sheet - Page 85
    Control Interface (PECI) Specification. 5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems Fan speed control solutions based on PECI utilize a TCONTROL value stored in the processor IA32_TEMPERATURE_TARGET MSR. The TCONTROL MSR uses the same offset temperature format as PECI though
  • Intel Q9300 | Data Sheet - Page 86
    Code Support The error codes supported for the processor GetTemp() command are listed in Table 5-6. Table 5-6. GetTemp0() Error Codes Error Code Description 8000h 8002h General sensor error Sensor is operational, but has detected a temperature below its operational range (underflow) § 86
  • Intel Q9300 | Data Sheet - Page 87
    the EXT_CONFIG Model Specific Register (MSR). This MSR allows for the disabling of a single core per die within the processor package. 6.2 Clock Control and Low Power States The processor allows the use of AutoHALT and Stop-Grant states to reduce power consumption by stopping the clock
  • Intel Q9300 | Data Sheet - Page 88
    INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume 3B: System Programming Guide, Part 2 for more
  • Intel Q9300 | Data Sheet - Page 89
    HALT Powerdown State Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled using the BIOS. When one of the processor cores executes the HALT instruction, that logical processor is halted; however, the other
  • Intel Q9300 | Data Sheet - Page 90
    serviced the processor will return to the Extended HALT state or Extended Stop Grant state. Sleep State The Sleep state is a low power state in which the processor the processor is not in these states is out of specification and may result in unapproved operation. In the Sleep state, the processor is
  • Intel Q9300 | Data Sheet - Page 91
    processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor additional platform level power savings. BCLK stop/restart timings on appropriate chipset-based platforms with to the Deep Sleep state but the core voltage is reduced to a lower level.
  • Intel Q9300 | Data Sheet - Page 92
    at reduced power consumption, the voltage is altered in step with the bus ratio. The following are key features of Enhanced Intel SpeedStep Technology: • Voltage/Frequency selection is software controlled by writing to processor MSR's (Model Specific Registers), thus eliminating chipset dependency
  • Intel Q9300 | Data Sheet - Page 93
    Boxed Processor Specifications 7 Boxed Processor Specifications 7.1 Introduction The Intel Core™2 Extreme processor QX9650, Intel Core™2 quad-core processor Q9000, Q9000S, Q8000, and Q8000S series will also be offered as an Intel boxed processor. Intel boxed processors are intended for system
  • Intel Q9300 | Data Sheet - Page 94
    Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 7-1 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow
  • Intel Q9300 | Data Sheet - Page 95
    power supply. A fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard. The power cable connector and pinout are shown in Figure 7-5. Baseboards must provide a matched power header to support the boxed processor. Table 7-1 contains specifications
  • Intel Q9300 | Data Sheet - Page 96
    Open drain type, pulse width modulated. 3. Fan will have pull-up resistor for this signal to maximum of 5.25 V. Max 12.6 - - - - - 28 Unit V Notes - A A - A Second pulses per fan 1 revolution kHz 2, 3 Figure 7-6. Baseboard Power Header Placement Relative to Processor Socket R110 [4.33
  • Intel Q9300 | Data Sheet - Page 97
    describes the cooling requirements of the fan heatsink solution used by the boxed processor. 7.4.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal
  • Intel Q9300 | Data Sheet - Page 98
    degrees from fan heatsink to fan heatsink. The internal chassis temperature should be kept below 38 ºC. Meeting the processor's temperature specification (see Chapter 5) is the responsibility of the system integrator. The motherboard must supply a constant +12 V to the processor's power header to
  • Intel Q9300 | Data Sheet - Page 99
    Tinlet temperature measured by a thermistor located at the fan inlet. For more details on specific motherboard requirements for 4-wire based fan speed control see the appropriate Thermal and Mechanical Design Guidelines (See Section 1.2). Boxed Intel® Core™2 Extreme Processor QX9650 Specifications
  • Intel Q9300 | Data Sheet - Page 100
    Figure 7-10. Space Requirements for the Boxed Processor (side view) 7.5.1 Boxed Intel® Core™2 Extreme Processor QX9650 Fan Heatsink Weight The Boxed Intel® Core™2 Extreme processor QX9650 fan heatsink weight will complies with the socket specifications. See Chapter 5 and the appropriate Thermal
  • Intel Q9300 | Data Sheet - Page 101
    Boxed Processor Specifications Figure 7-12. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view) § Datasheet 103
  • Intel Q9300 | Data Sheet - Page 102
    Boxed Processor Specifications 104 Datasheet
  • Intel Q9300 | Data Sheet - Page 103
    use in debugging Intel® Core™2 Extreme processor QX9000 series, Intel® Core™2 Quad processor Q9000, Q9000S, Q8000, and Q8000S series systems. Tektronix and Agilent should be contacted to get specific electrical performance of the FSB; therefore, it is critical to obtain electrical load models from
  • Intel Q9300 | Data Sheet - Page 104
    Debug Tools Specifications 106 Datasheet
  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
Document Number: 318726-010
Intel
®
Core™2 Extreme Processor
QX9000
Δ
Series, Intel
®
Core™2 Quad
Processor Q9000
Δ
, Q9000S
Δ
, Q8000
Δ
,
and Q8000S
Δ
Series
Datasheet
— on 45 nm process in the 775 land package
August 2009