LG KM710 Service Manual - Page 39

Bluetooth circuit Description

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3. HW Circuit Description 3.6.3 Bluetooth circuit Description • Single chip 90 nm CMOS Bluetooth ROM solution • Bluetooth 1.1, 1.2 and 2.0 specification compliant - up to HCI level. • Enhanced Data Rate (2&3 Mbps) • Future support for Bluetooth 2005 core release (software upgrade when Bluetooth specification will be available) • Enhanced host interfaces (UART, SDIO) • Very low power consumption • Pin-to-pin compatible with BRF6150 • On-chip Digital Radio Processor (DRP) o Integrated 2.4 GHz RF transceiver o All digital PLL transmitter with digitally controlled oscillator o Near zero IF architecture o On-chip TX/RX switch o Support for Class 1 applications • Embedded ARM7TDMIE Microprocessor System On Chip o High rate H4 UART HCI o High rate HCI Three Wire UART Transport Layer (H5) o SDIO transport layer o Flexible PCM and I2S interfaces: full flexibility for data order, sampling and positioning o Automatic clock detection mechanism o Patch trap mechanism that enables feature changes in ROM (ROM updates, improvements) • On-chip Power Management adapted to cellular application o Direct connection to battery or external LDO 1.7 to 5.4V o IO supply voltage - 1.62 - 1.89V o Power saving mode o Shut-Down mode to minimize power consumption when Bluetooth is not used • Temperature detection and compensation mechanism ensures minimal variation in the RF performance over the whole temperature range • Seamless integration with TI OMAP™ application processor and GSM-GPRSUMTS chipset • Enhanced support for WLAN Co-existence (bandwidth sharing, antenna sharing) • Spurious emissions compatible with GPS applications • 5 external capacitors and balun/matching network required - total PCB area required only 45 mm2 (BGA package) • Package: 4.5x4.5 mm size, 0.5 mm ball pitch, pb-free Micro Star Junior BGA package. • Stacked RAM support with the same footprint as the ROM device (for development phase only) • TI proprietary low power scan achieves paging and inquiry scans with fast RSSI algorithm, at 1/3rd normal power. LGE Internal Use Only - 40 - Copyright © 2008 LG Electronics. Inc. All right reserved. Only for training and service purposes

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- 40 -
3. HW Circuit Description
LGE Internal Use Only
Copyright © 2008 LG Electronics. Inc.
All right reserved.
Only for training and service purposes
3.6.3 Bluetooth circuit Description
• Single chip 90 nm CMOS Bluetooth ROM solution
• Bluetooth 1.1, 1.2 and 2.0 specification compliant - up to HCI level.
• Enhanced Data Rate (2&3 Mbps)
• Future support for Bluetooth 2005 core release (software upgrade when Bluetooth specification will
be available)
• Enhanced host interfaces (UART, SDIO)
• Very low power consumption
• Pin-to-pin compatible with BRF6150
• On-chip Digital Radio Processor (DRP)
o Integrated 2.4 GHz RF transceiver
o All digital PLL transmitter with digitally controlled oscillator
o Near zero IF architecture
o On-chip TX/RX switch
o Support for Class 1 applications
• Embedded ARM7TDMIE Microprocessor System On Chip
o High rate H4 UART HCI
o High rate HCI Three Wire UART Transport Layer (H5)
o SDIO transport layer
o Flexible PCM and I2S interfaces: full flexibility for data order, sampling and positioning
o Automatic clock detection mechanism
o Patch trap mechanism that enables feature changes in ROM (ROM updates, improvements)
• On-chip Power Management adapted to cellular application
o Direct connection to battery or external LDO 1.7 to 5.4V
o IO supply voltage - 1.62 - 1.89V
o Power saving mode
o Shut-Down mode to minimize power consumption when Bluetooth is not used
• Temperature detection and compensation mechanism ensures minimal variation in the RF
performance over the whole temperature range
• Seamless integration with TI OMAP™ application processor and GSM-GPRSUMTS chipset
• Enhanced support for WLAN Co-existence (bandwidth sharing, antenna sharing)
• Spurious emissions compatible with GPS applications
• 5 external capacitors and balun/matching network required - total PCB area required only 45 mm2
(BGA package)
• Package: 4.5x4.5 mm size, 0.5 mm ball pitch, pb-free Micro Star Junior BGA package.
• Stacked RAM support with the same footprint as the ROM device (for development phase only)
• TI proprietary low power scan achieves paging and inquiry scans with fast RSSI algorithm, at 1/3rd
normal power.