Lenovo ThinkPad 560X TP 560Z Technical Reference Manual - Page 20

Description, Microprocessor, Cache Memory Operation

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Description This section describes the microprocessor, connectors, memory subsystems, and miscellaneous system functions and ports for the ThinkPad computers. You can find additional information about these topics in IBM Personal System/2 Hardware Interface Technical Reference-AT-Bus Subsystems. Microprocessor The ThinkPad 560Z computer uses the Intel® Mobile Pentium® II 233-MHz or 300-MHz processor with MMX™ technology. The processor has a 32-bit address bus and a 64-bit data bus. It is software-compatible with all previous microprocessors. The processor has an internal, split data and instruction, 32-KB write-back cache. It includes pipelined math coprocessor functions and superscalar architecture (two execution units). Cache Memory Operation The cache memory in the Intel Pentium microprocessor enables the microprocessor to read instructions and data much faster than if the microprocessor had to access system memory. When an instruction is first used or data is first read or written, it is transferred to the cache memory from main memory. This enables future accesses to the instructions or data to occur much faster. The cache is disabled and empty when the microprocessor comes out of the reset state. The cache is tested and enabled during the power-on self-test (POST). The cache memory in the Intel Pentium microprocessor is loaded from system memory in 32-byte increments, each referred to as a cache line. A cache line is aligned on a paragraph boundary. A reference to any byte contained in a cache line results in the entire line being read into the cache memory (if the data was not already in the cache). When the microprocessor gives up control of the system bus, the cache memory enters "snoop" mode and monitors all write and read operations. If memory data is written to a location in the cache and the cache line is in the "modified" state, the corresponding cache line is written back to system memory and is invalidated. 2-2 ThinkPad 560Z System Board

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Description
This section describes the microprocessor, connectors, memory
subsystems, and miscellaneous system functions and ports for the
ThinkPad computers.
You can find additional information about
these topics in
IBM Personal System/2 Hardware Interface Technical
Reference–AT-Bus Subsystems
.
Microprocessor
The ThinkPad 560Z computer uses the Intel
Mobile Pentium
II
233-MHz or 300-MHz processor with MMX
technology.
The processor has a 32-bit address bus and a 64-bit data bus.
It is
software-compatible with all previous microprocessors.
The
processor has an internal, split data and instruction, 32-KB
write-back cache.
It includes pipelined math coprocessor functions
and superscalar architecture (two execution units).
Cache Memory Operation
The cache memory in the Intel Pentium microprocessor enables the
microprocessor to read instructions and data much faster than if the
microprocessor had to access system memory.
When an instruction
is first used or data is first read or written, it is transferred to the
cache memory from main memory.
This enables future accesses to
the instructions or data to occur much faster.
The cache is disabled and empty when the microprocessor comes
out of the reset state.
The cache is tested and enabled during the
power-on self-test (POST).
The cache memory in the Intel Pentium microprocessor is loaded
from system memory in 32-byte increments, each referred to as a
cache line
.
A cache line is aligned on a paragraph boundary.
A
reference to any byte contained in a cache line results in the entire
line being read into the cache memory (if the data was not already in
the cache).
When the microprocessor gives up control of the system
bus, the cache memory enters “snoop” mode and monitors all write
and read operations.
If memory data is written to a location in the
cache and the cache line is in the “modified” state, the corresponding
cache line is written back to system memory and is invalidated.
2-2
ThinkPad 560Z System Board