Oki ML421 Maintenance Manual - Page 127

Circuit Description

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2.2 Circuit Description A block diagram is shown in Figure C-1. 80C51 RST OCS P1 P3 P0 P2 TD RD IF WR ADR latch LS245 DB0 to DB9 ROM 64Kbit Receiver Driver Oki Data CONFIDENTIAL CN1 75188 TD 75189 RD ADR bus ADR/data bus RAM 64Kbit +5 VD +12VDC -8VDC +5 V ±9 V power supply circuit +9 V -9 V +5V 0V Figure C-1 Block Diagram Serial data control line Bus line Control line 2.2.1 Operation at power on After power is turned on, an RST OUT signal is sent from the printer control board to reset the printer. When the reset is canceled, the 80C51 CPU performs initialization. Initialization consists of setting the 80C51 timer, and setting the serial mode. 2.2.2. RS-232C interface The DTR, SSD, TD and RTS signals output by the 80C51 are converted to RS-232C signals by line driver 75188 (Q1) and sent to the interface. In addition, signals DSR, CTS, CD, and RD on the RS232C interface are converted to TTL level by line receiver 75189 (Q2) and input to the 80C51. 42113901 Rev.2 127 /

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42113901
Rev.2
127 /
Oki
Data
CONFIDENTIAL
OCS
P1
P2
P0
P3
TD
RD
IF WR
LS245
ROM
64Kbit
RD
TD
RAM
64Kbit
Driver
+5 VD
+12VDC
-8VDC
+5 V
+9 V
–
9 V
+5V
0V
±
9 V power
supply circuit
Serial data
control line
Bus line
Control line
ADR latch
Receiver
DB0 to DB9
ADR/data bus
ADR bus
80C51
RST
CN1
75188
75189
Figure C-1
Block Diagram
2.2
Circuit Description
A block diagram is shown in Figure C-1.
2.2.1
Operation at power on
After power is turned on, an RST OUT signal is sent from the printer control board to reset the
printer. When the reset is canceled, the 80C51 CPU performs initialization. Initialization consists
of setting the 80C51 timer, and setting the serial mode.
2.2.2.
RS-232C interface
The DTR, SSD, TD and RTS signals output by the 80C51 are converted to RS-232C signals
by line driver 75188 (Q1) and sent to the interface.
In addition, signals DSR, CTS, CD, and RD on the RS232C interface are converted to TTL level
by line receiver 75189 (Q2) and input to the 80C51.