Toshiba XM-7002B Product Specification - Page 21

6.2.4.Timing of Host Interface (Ultra DMA ) Figure 12 shows the Host Interface Ultra DMA word Timings tMLI DMARQ tUI DMACKSTOP DMARDY STROBE DD (15:0) tACK tFS tENV t2CYC tCYC tCYC t2IORDY t2AD tDVS tDVH tDVS tDVH tDVS tDVH tRP tLI tRFS tACK tDVS tDVH CRC t2CYC Ultra DMA Mode 2 timing parameters min (ns) max (ns) Typical Sustained Average Cycle time tCYC Cycle time tDVS Data Setup time tDVH Data Hold time tUI Unlimited Interlock time tACK Setup and Hold Time for DMACK- tENV Envelope time t2AD Minimum Delay time for Driver t2IORODY Minimum time for DMACK- tFS First STROBE time tRFS Ready-to-Final STROBE time tRP Ready-to-Pause time tLI Limited Iuterlock time tMLI Interlock with minimum Min time (ns) 120 55 34 6 0 20 20 0 20 0 100 0 20 Figure 12 Host Interface Timing (Ultra DMA) Max time (ns) 70 170 50 150 17/27 XM-7002B Rev.1.0