Via EPIA-SP8000E User Manual - Page 81

DRAM Clock, DRAM Timing, SDRAM CAS Latency

Get Via EPIA-SP8000E - VIA Motherboard - Mini ITX PDF manuals and user guides View all Via EPIA-SP8000E manuals
Add to My Manuals
Save this manual to your list of manuals

Page 81 highlights

BIOS Setup FREQUENCY / VOLTAGE CONTROL Phoenix - AwardBIOS CMOS Setup Utility Frequency / Voltage Control DRAM Clock DRAM Timing SDRAM CAS Latency Bank Interleave Precharge to Active(Trp) Active to Precharge(Tras) Active to CMD(Trcd) REF to ACT/REF to REF(Trfc) ACT(0) to ACT(1) (TRRD) [166 MHz] [Auto By SPD] 2.5 Disabled 4T 9T 4T 15T 3T Item Help Menu Level Spread Spectrum [Enabled] : Move Enter: Select F5: Previous Values +/-/PU/PD: Value F10: Save F6: Fail-Safe Defaults ESC: Exit F1: General F7: Optimized Defaults Help DRAM Clock The chipset supports synchronous and asynchronous mode between host clock and DRAM clock frequency. Settings: [66 MHz, 100 MHz, 133 MHz, 166 MHz, By SPD] DRAM Timing The value in this field depends on the memory modules installed in your system. Changing the value from the factory setting is not recommended unless you install new memory that has a different performance rating than the original modules. Settings: [Manual, By SPD] SDRAM CAS Latency This item is for setting the speed it takes for the memory module to complete a command. Generally, a lower setting will improve the performance of your system. However, if your system becomes less stable, you should change it to a higher setting. This field is only available when "DRAM Timing" is set to "Manual". Settings: [2, 2.5] 73

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
BIOS Setup
73
F
REQUENCY
/
V
OLTAGE
C
ONTROL
: Move
F5: Previous Values
F6: Fail-Safe Defaults
F7: Optimized Defaults
Enter: Select
+/-/PU/PD: Value
F10: Save
ESC: Exit
F1: General
Help
Menu Level
Item Help
DRAM Clock
[166 MHz]
DRAM Timing
[Auto By SPD]
Bank Interleave
Disabled
Precharge to Active(Trp)
4T
Active to Precharge(Tras)
9T
Active to CMD(Trcd)
4T
REF to ACT/REF to REF(Trfc)
15T
ACT(0) to ACT(1) (TRRD)
3T
SDRAM CAS Latency
2.5
Frequency / Voltage Control
Phoenix - AwardBIOS CMOS Setup Utility
Spread Spectrum
[Enabled]
DRAM Clock
The chipset supports synchronous and asynchronous mode between host
clock and DRAM clock frequency.
Settings: [66 MHz, 100 MHz, 133 MHz, 166 MHz, By SPD]
DRAM Timing
The value in this field depends on the memory modules installed in your
system.
Changing the value from the factory setting is not recommended
unless you install new memory that has a different performance rating than
the original modules.
Settings: [Manual, By SPD]
SDRAM CAS Latency
This item is for setting the speed it takes for the memory module to
complete a command.
Generally, a lower setting will improve the
performance of your system.
However, if your system becomes less stable,
you should change it to a higher setting.
This field is only available when
“DRAM Timing” is set to “Manual”.
Settings: [2, 2.5]